Method and apparatus for power mode transition in a multi-thread processor

A method of transitioning from an active mode to a low power mode in a processor including a first logical processor associated with a first identifier and a second logical processor associated with a second identifier, comprising:

• associating said first and second logical processors with a common clock;
• receiving an instruction to enter the low power mode from a chipset coupled to said processor;
• issuing a first indication to said chipset, including the first identifier, that the first logical processor has entered the low power mode;
• issuing a second indication to said chipset, including the second identifier, that the second logical processor has entered the low power mode and
• in response to the issuance of said first and second indications, receiving a signal from said chipset and entering said low power mode.

A method of monitoring the power mode of a processor having a first logical processor associated with a first identifier and a second logical processor associated with a second identifier, comprising:

• associating said first and second logical processors with a common clock;
• receiving a first indication at a chipset coupled to said processor, including the first identifier, that the first logical processor has entered a power mode;
• receiving a second indication at a chipset coupled to said processor, including the second identifier, that the second logical processor has entered the power mode;
• instructing the processor to enter a second power mode when both the first and the second indications have been received.

A method of monitoring the power modes of a first processor having a first logical processor associated with a first identifier and a second logical processor associated with a second identifier and a second processor having a third logical processor associated with a third identifier and a fourth logical processor associated with a fourth identifier, comprising:

• associating said first and second logical processors with a common clock;
• receiving an indication at a chipset that the first processor has entered a power mode;
• comprising:
• receiving a first indication, including the first identifier, that the first logical processor has entered the power mode, and
• receiving a second indication, including the second identifier, that the second logical processor has entered the power mode;
• and
• receiving an indication at said chipset that the second processor has entered the power mode comprising:
• receiving a third indication, including the third identifier, that the third logical processor has entered the power mode, and
• receiving a fourth indication, including the fourth identifier, that the fourth logical processor has entered the power mode.

A method of transitioning a processor having an active mode, a first low power mode and a second low power mode, the processor also having a first logical processor associated with a first identifier and a second logical processor associated with a second identifier, comprising:

• associating said first and second logical processors with a common clock;
• receiving a first indication at a chipset coupled to said processor, including the first identifier, that the first logical processor has entered the first low power mode;
• receiving a second indication at said chipset, including the second identifier, that the second logical processor has entered the first low power mode;
• and
• transitioning the processor to the second low power mode by sending a signal from said chipset when both the first and second indications have been received.

A processor, comprising:

• a first logical processor coupled to a chipset configured to issue a first indication to said chipset, including a first identifier associated with said first logical processor, that said first logical processor has entered a logical power mode;
• a second logical processor configured to issue a second indication to said chipset, including a second identifier associated with said second logical processor, that said second logical processor has entered the logical power mode;
• a clock to be utilized by said first and second logical processors;
• and
• a processor controller configured to instruct said first and second logical processors to enter a second power mode when the first and the second indications have been received.

A computer system, comprising:

• a processor configured to issue a first indication, including a first identifier associated with a first logical processor, that the first logical processor has entered a first power mode and further configured to issue a second indication, including a second identifier associated with a second logical processor, that the second logical processor has entered the first power mode;
• a clock to be utilized by said first and second logical processors;
• and
• a processor controller coupled to said processor by a bus and configured to instruct said processor to enter a second power mode when the first and the second indications have been received from said processor.

An article of manufacture comprising a computer readable medium having stored thereon instructions which, when executed by a processor, cause the processor to perform steps to enter a power mode, comprising:

• issuing a first indication to a chipset coupled to said processor, including a first identifier associated with a first logical processor in the processor, that the first logical processor has entered a power mode;
• issuing a second indication to said chipset, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode;
• a clock to be utilized by said first and second logical processors;
• and
• in response to the issuance of said first and second indications, receiving a signal from said chipset and entering said power mode.