System and method for efficient processing of instructions using control unit to select operations

A processor comprising:

• a control unit having a mode bit to control execution of an instruction decoded by a decode unit;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction alters the mode bit, if so, executing the current instruction but stalling all following dependant instructions affected by the mode bit until execution of the current instruction is complete.

A processor comprising:

• a control unit having a mode bit to control execution of an instruction decoded by a decode unit;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction alters the mode bit, if so, setting the mode bit to select use of the second circuit for processing the instruction, determining if the mode bit was set correctly upon processing of the instruction, if not, resetting the mode bit to select use of the first circuit for reprocessing the instruction.

A processor comprising:

• a control unit having a mode bit to control execution of an instruction decoded by a decode unit;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction alters the mode bit, if so, setting the mode bit to select use of the first circuit for processing a current instruction, determining if the mode bit was set correctly upon processing of the instruction, if not, resetting the mode bit to select use of the second circuit for processing a following instruction.

A method comprising:

• controlling execution of an instruction decoded by a decode unit;
• and
• providing, first and second circuits to perform first and second operations under first and second conditions, respectively. the first and second circuits excluding the decode unit;
• said controlling comprises determining if processing of the instruction is to be performed under the second condition, if so, selecting the second circuit to process the instruction, otherwise selecting the first circuit to process the instruction.

A method comprising:

• controlling execution of an instruction decoded by a decode unit;
• and
• providing first and second circuits to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said controlling comprises determining if the instruction alters an operational mode, if so, executing the current instruction but stalling all following dependent instructions affected by the mode bit until execution of the current instruction is complete.

A method comprising:

• controlling execution of an instruction decoded by a decode unit;
• and
• providing first and second circuits to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said controlling comprises
• determining if the instruction alters an operational mode, if so, selecting the second circuit for processing the instruction;
• and
• determining if selection of the second circuit for processing the instruction was in accordance with the alteration of the operational mode upon processing of the instruction, if not, altering the operational mode to select the first circuit for re-processing the instruction.

A method comprising:

• controlling execution of an instruction decoded by a decode unit;
• and
• providing first and second circuits to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said controlling comprises
• determining if the instruction alters an operational mode, if so, altering the operational mode to select the first circuit for processing a current instruction;
• and
• determining if the operational mode was correctly altered upon processing of the instruction, if not, resetting the operational mode to select use of second circuit for processing a following instruction.

A processing system comprising:

• a decode unit to decode an instruction;
• a control unit coupled the decode unit to control execution of the instruction;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction is to be performed under the second condition, if so, selecting the second circuit to process said instruction, otherwise selecting said first circuit to process said instruction.

A processing system comprising:

• a decode unit to decode an instruction;
• a control unit coupled the decode unit to control execution of the instruction, the control unit having a mode bit;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction alters the mode bit, if so, executing the current instruction but stalling all following dependent instructions affected by the mode bit until execution of the current instruction is complete.

A processing system comprising:

• a decode unit to decode an instruction;
• a control unit coupled the decode unit to control execution of the instruction, the control unit having a mode bit;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction alters the mode bit, if so, setting the mode bit to select use of the second circuit for processing the instruction, determining if the mode bit was set correctly upon processing of the instruction, if not, resetting the mode bit to select use of the first circuit for re-processing the instruction.

A processing system comprising:

• a decode unit to decode an instruction;
• a control unit coupled the decode unit to control execution of the instruction, the control unit having a mode bit;
• and
• first and second circuits coupled to the control unit to perform first and second operations under first and second conditions, respectively, the first and second circuits excluding the decode unit;
• said control unit determining if the instruction alters the mode bit, if so, setting the mode bit to select use of the first circuit for processing a current instruction, determining if the mode bit was set correctly upon processing of the instruction, if not, resetting the mode bit to select use of the second circuit for processing a following instruction.