Computer system having an instruction for probing memory latency

Abstract

A computer system includes a data structure that maintains availability status for registers of a processor of the computer system, wherein the availability status indicates whether an instruction attempting to read a particular register will stall. The computer system also includes instruction decode and execution circuitry that is capable of decoding and executing one or more instructions that alter a path of program execution based on the availability status of one or more of the registers. In one embodiment, a latency probe instruction retrieves the availability status of a register from the data structure and stores the availability status in a register. Thereafter, a conditional branch instruction determines the path of program execution based on the availability status stored in the register. In another embodiment, a conditional branch instruction queries the data structure directly to determine the availability status of a register, and determines the execution path based on the availability status. By exposing the latency of memory operations to programs, a compiler can schedule alternate threads of execution based on varying latencies. By scheduling alternate threads of execution based on the availability of the contents of a register, stalling is minimized. The present invention can also be used by a compiler to optimize code. The present invention is relatively easy to implement in many modern computer architectures that support “stall on use” techniques and include “non-blocking caches”.

Dependencies are inferred from the claim text.