Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system

Abstract

A computer system includes a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). According to one embodiment, the host processor executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor communicates with the emulation coprocessor to cause the emulation coprocessor to execute the foreign application program. The computer system also includes a bus bridge coupled to the host processor and the emulation coprocessor. The bus bridge provides access to main memory both for the host processor and the emulation coprocessor, and provides for coherency between the host processor and emulation coprocessor. Preferably in one particular embodiment, the bus bridge may be a bus bridge designed for a symmetric multiprocessing system including multiple host processors. By providing an emulation coprocessor having a bus interface which is electrically and logically identical to the bus interface provided by the host processor, the emulation coprocessor may be inserted into a processor slot within a symmetric multiprocessing system to form a computer system which employs high performance hardware support for a foreign instruction set architecture. The host processor may control the emulation coprocessor via software, allowing the coprocessor system to be realized without additional hardware.

Dependencies are inferred from the claim text.