RISC CPU instructions particularly suited for decoding digital signal processing applications
AssigneesSony Corporation, Sony Electronics Inc.
InventorsShirish Gadre, Mazin S. Khurshid
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AssigneesSony Corporation, Sony Electronics Inc.
InventorsShirish Gadre, Mazin S. Khurshid
Estimating the term…
A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.
An integrated circuit device circuit arrangement for processing multimedia data, the circuit arrangement comprising a processing core including:
An integrated circuit device circuit arrangement for processing multimedia data, the circuit arrangement comprising a processing core including:
An integrated circuit device circuit arrangement for processing multimedia data, the circuit arrangement comprising a processing core including:
Dependencies are inferred from the claim text.