Processor method and apparatus for performing single operand operation and multiple parallel operand operation

A processor comprising:

• n-bit register circuitry for holding instruction operands;
• instruction decode circuitry to decode processor instructions from an instruction stream;
• and
• arithmetic logic (AL) circuitry including a plurality of arithmetic logic units (ALU1to ALUk),
• each of the arithmetic logic units ALUi (for i=1 to k) separately operable to perform a separate single operation on at least one mi-bit operand provided from the n-bit register circuitry, responsive to first separate single processor instructions decoded by the instruction decode circuitry,
• wherein each mi<n (for i=1 to k),
• wherein each of ALUi (for i=1 to k) is not operable to perform any single operation on an operand larger than mi bits, and
• wherein the sum of all mi (for i=1 to k) for the ALU's is less than or equal to n,
• the ALU's further being collectively operable to perform multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry, responsive to a second single instruction decoded by the instruction decode circuitry,
• each of the ALU's having an integer pipe circuitry each operable to perform multiple bit operation,
• said ALU having a plurality of integer pipe circuitries, each operable to perform multiple bit operation, wherein
• in the case a plurality of single operation instructions are simultaneously issued, a plurality of single operations are operated in parallel using said plurality of integer pipe circuitries,
• in the case a single operation instruction and said multiple parallel operation instructions are simultaneously issued and said multiple parallel operation instructions are to be operated with priority, performance of said single operation instruction is halted until performances of said multiple parallel operation instructions are completed, and
• in the case a single operation instruction and said multiple parallel operation instructions are simultaneously issued and said single operation instruction is to be operated with priority, performances of said multiple parallel operation instructions are halted until performance of said single operation instruction is completed.

A method of processing instructions by a processor, comprising:

• holding n-bit instruction operands in n-bit register circuitry;
• sequentially decoding processor instructions from an instruction stream;
• a first performing step of performing a single operation on at least one m-bit operand provided from the n-bit register circuitry, responsive to a first decoded single processor instruction, wherein m<n, and not performing any single operation on an operand larger than bits;
• and
• a second performing step of performing multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry, responsive to a second decoded single instruction;
• wherein the first performing step is performed by first m-bit integer pipe circuitry that is operable to perform the single operation on an m-bit operand and by second j-bit integer pipe circuitry that is operable to perform the single operation on a j-bit operand, and the second performing step is performed by the first m-bit integer pipe circuitry and the second j-bit integer pipe circuitry to perform the multiple parallel operations on an m+j bit operand.

A processor comprising:

• n-bit register circuitry for holding instruction operands;
• instruction decode circuitry to decode processor instructions from an instruction stream;
• and
• arithmetic logic (AL) circuitry including a plurality of arithmetic logic units (ALU1 to ALUk),
• each of the arithmetic logic units ALUi (for i=1 to k) separately operable to perform a separate single operation on at least one mi-bit operand provided from the n-bit register circuitry, responsive to first separate single processor instructions decoded by the instruction decode circuitry,
• wherein each mi<n (for i=1 to k),
• wherein each of ALUi (for i=1 to k) is not operable to perform any single operation on an operand larger than mi bits, and
• wherein the sum of all mi (for i=1 to k) for the ALU's is less than or equal to n the ALU's further being collectively operable to perform multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry, responsive to a second single instruction decoded by the instruction decode circuitry.

A method comprising:

• holding instruction operands in n-bit register circuitry;
• decoding processor instructions from an instruction stream;
• and
• a first performing step of performing a separate single operation on at least one mi-bit operand provided from the n-bit register circuitry, responsive to first separate single decode processor instructions,
• wherein each mi<n (for i=1 to k), using mi-bit integer pipe circuitry that is operable to perform the single operation,
• but not performing any single operation on an operand larger than mi bits, and
• wherein the sum of all mi (for i=1 to k) is less than or equal to n
• a second performing step of performing multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry, responsive to a second single decoded instruction using all the mi-bit (for i=1 to k) integer pipe circuitries.

A processor comprising:

• n-bit register circuitry for holding instruction operands;
• instruction decode circuitry to sequentially decode processor instructions from an instruction stream;
• and
• arithmetic logic (AL) circuitry to perform one of:
• a single operation at least one m-bit operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m<n and wherein the AL circuitry is not operable to perform any single operation on an operand larger than m bits, and
• multiple parallel operations on at least two portions of the one n-bit operand provided from the n-bit register circuitry, responsive to a second single instruction decoded by the instruction decode circuitry;
• said AL circuitry having a plurality of integer pipe circuitries, each operable to perform multiple bit operation, wherein:
• in the case a plurality of single operation instructions are simultaneously issued, a plurality of single operations are operated in parallel using said plurality of integer pipe circuitries,
• in the case a single operation instruction and said multiple parallel operation instructions are simultaneously issued and said multiple parallel operation instructions are to be operated with priority, performance of said single operation instruction is halted until performances of said multiple parallel operation instructions are completed, and
• in the case a single operation instruction and said multiple parallel operation instructions are simultaneously issued and said single operation instruction is to be operated with priority, performances of said multiple parallel operation instructions are halted until performance of said single operation instruction is completed.