Information processing apparatus with improved multiple memory access and control

An information processing apparatus comprising:

• a first CPU card and a second CPU card forming first and second systems, respectively, each CPU card including a CPU, a memory, and a data bus connecting said CPU and said memory, respectively;
• a single inter-system data bus connecting said first CPU card to said second CPU card;
• first gate means and second gate means for connecting/disconnecting said inter-system data bus and one of said first data bus and said second data bus, respectively;
• gate controlling means respectively included in said first CPU card and said second CPU card, respectively, for decoding the address output from said first CPU and said second CPU, respectively, and to set said first gate means and said second gate means in closed states when the decoded result indicates that writing of data is to be performed by either of said first CPU and said second CPU into both of said first memory and said second memory;
• to set said first gate means and said second gate means in closed states when the decoded result indicates that reading of data is to be performed by either of said first CPU and said second CPU into the memory of the other CPU card;
• and
• to set said first gate means and said second gate means in open states when the decoded result indicates that reading of data is to be performed by at least either one of said first CPU and said second CPU reads data from the memory of the CPU card of the CPU performing the reading;
• writing/reading control means included in said first CPU card and said second CPU card, respectively, for decoding the address output from said first CPU and said second CPU, respectively, and
• to set both of said first memory and said second memory in states enabling writing when the decoded result indicates that writing of data is to be performed by either of said first CPU and said second CPU into both of said first memory and said second memory;
• to set said memory of the CPU card of the CPU not performing reading in a state enabling reading when the decoded result indicates that reading of data is to be performed by either of said first CPU and said second CPU into the memory of the CPU card of the CPU not performing the reading;
• and
• to set the memory of the CPU card of the CPU performing reading in a state enabling reading when the decoded result indicates that reading of data is to be performed by at least either one of said first CPU and said second CPU from the memory of the CPU card of the CPU performing reading;
• to set only one of said first memory and said second memory in a state enabling reading.

An information processing apparatus comprising:

• a first CPU and a second CPU;
• a single CPU bus gate connecting said first CPU and said second CPU;
• a first bus and a second bus gate connecting or disconnecting each of the first CPU and the second CPU, and the single bus, respectively;
• a first memory and a second memory connected to the single CPU bus for operation as duplex memories, said memories having different addresses;
• a gate means provided between the connection node of the first memory and the CPU bus and the connection node of the second memory and the CPU bus;
• an access control means for controlling the gate means so that the gate means is in an open state when either of the first CPU and the second CPU outputs an address of the memory of the CPU that outputs the address itself.

An information processing apparatus comprising:

• a first CPU and a second CPU;
• a single CPU bus connecting between the first CPU and the second CPU;
• a plurality of memories connected to the single CPU bus for operation as duplex memories;
• a plurality of gate means connected between the connection nodes of the CPU bus with the plurality of memories;
• an access control means for controlling, when either of said first CPU and said second CPU outputs an address of a required one among said plurality of memories, the gate means so that only the gate means connected between the selected memory and the memory that is closest to the selected memory at the side of the other CPU, is in an open state and all the other gate means are in closed states.