Electronically moveable terminator and method for using same in a memory system
AssigneeRambus Inc.
InventorJames Anthony Gasbarro
Life of this patent
Estimating the term…
Abstract
An expandable memory system having a plurality of memory devices, each with an electronically activated terminator is disclosed. Also a method for detecting the last memory device arranged along a data bus connecting a memory controller with the memory devices, and activating its active terminator is disclosed.
Claims17
A memory system comprising:
- a memory controller connected to a plurality of memory devices via a data bus, wherein the data bus terminates in the memory controller at a first end and at a resistive terminator at a second end;
- the data bus comprising a first portion having a first impedance, and a second portion having a second impedance;
- wherein at least one of the plurality of memory devices comprises an active terminator having a third impedance, such that upon activation of the active terminator, the third inpedance is placed in parallel with the second impedance to balance the first and second impedances.
A memory system comprising:
- a memory controller connected to a first end of a data bus;
- a resistive terminator connected to a second end of the data bus;
- wherein the data bus comprises a plurality of slots arranged between the first and second ends of the data bus, each slot being adapted to receive a memory module and comprising an active terminator responsive to a control signal from the memory controller.
A method of balancing impedance between first and second portions of a data bus in a memory system, the memory system comprising a memory controller and a plurality of memory devices connected via a serial initialization line and a channel including the data bus, wherein the data bus connects the memory controller at a first end and a resistive terminator at a second end, the method comprising:
- determining in the memory controller one memory device located last on the data bus closest to the resistive terminator;
- and,
- activating an active terminator in the one memory device to balance the first and second portions of the data bus.
A method of operating a memory system wherein the memory system comprises;
- a memory controller connected to a first end of a data bus, and a resistive terminator connected to second end of the data bus, wherein the data bus comprises a first portion having a first impedance, and a second portion having a second impedance,
- a plurality of memory devices arranged along the data bus between the first and second ends from a first memory device closest to the memory controller to a last memory device closest to the resistive terminator,
- wherein each one of the plurality of memory devices comprises an active terminator having a third impedance;
- the method comprising:
- detecting the presence of the last memory device along the data bus;
- and
- activating the active terminator in the last memory device to combine the third impedance with the second impedance to balance the first and second impedances.
Dependencies are inferred from the claim text.