Low-power pulse-shaping digital filters
AssigneePentomics, Inc.
InventorsAlan N. Willson, Jr., Larry S. Wasserman
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AssigneePentomics, Inc.
InventorsAlan N. Willson, Jr., Larry S. Wasserman
Estimating the term…
A method, apparatus, article of manufacture, and a memory structure for low power digital filtering. The method comprises the steps of successively delaying each of the input values {x0,x1, . . . ,xN−1} to create tap values {t0,t1, . . . ,tN−1}, multiplying each of the tap values {t0,t1, . . . ,tN−1} by A•{h0,h1, . . . ,hN−1} to produce {At0h0,At1h1, . . . ,AtN−1hN−1}wherein values {h0,h1, . . . ,hN−1} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency in filtering the input data stream, summing the values {At0h0,At1h1, . . . ,AtN−1hN−1} to produce ∑ k = 0 N - 1 At k h k , biasing the summed values {At0h0,At1h1, . . . ,AtN−1hN−1} to compensate for the modified filter tap values and to produce a digital filter output. The article of manufacture comprises means for performing the above method steps. The apparatus comprises an interconnected series of k stages wherein k={1,2, . . . ,N−1}. Each of the stages comprises a delay element Zk−1 having a delay element input and a delay element output, a weighting element having a weighting element input and a weighting element output, wherein a gain of the weighting element is selected to be a product of a gain hk required to achieve a desired digital filter response, and a factor A selected to improve computational efficiency, and a summation element having a first summation element input, a second summation element input, and a summation element output. A bias summation element is coupled between the leading gain element and the first stage summation element, for adding a bias to compensate for the factored weighting element gains.
A finite impulse response digital filter for filtering input values, comprising:
A method of filtering a series of mapped input data values {x0,x1, . . . ,xN−1}, comprising the steps of:
A method of processing a series of input values to produce a series of output values having a desired output characteristic by implementing a sum of a series of delayed, mapped, and weighted input values, comprising the steps of:
An apparatus for computing the response of a digital filter by implementing a sum of a series of delayed, mapped, and weighted input values, comprising:
A program storage device, readable by a computer, tangibly embodying one or more programs of instructions executable by the computer to perform method steps of filtering an input data stream {x0,x1, . . . ,xN−1}, the method steps comprising the steps of:
A method of filtering a series of mapped input data values {x0,x1, . . . ,XN−1}, comprising the steps of:
A method of reducing the computations required in a digital filter implementing a sum of a series of weighted and delayed input data values, comprising the steps of:
A method of filtering a series of mapped input data values {x0,x1, . . . ,xN−1}, comprising the steps of:
A method of filtering a series of mapped input data values {x0,x1, . . . ,xN−1} comprising the steps of:
An apparatus for filtering a series of mapped input data values {x0,x1, . . . ,xN−1}, comprising:
A method of processing a series of input values to produce a series of output values having a desired output characteristic comprising the steps of:
Dependencies are inferred from the claim text.