Apparatus for partial logical shifts and method therefor

A method of generating m-bit partial logical shifts of a logical signal comprising the steps of:

• rotating each portion of a plurality of portions of said logical signal by m-bits, thereby forming a plurality of corresponding rotated portions;
• masking each said rotated portion with a preselected mask signal;
• masking each said rotated portion with a complementary mask formed by complementing said preselected mask signal;
• and
• logically combining each logical output from said step of masking with a preselected mask with a preselected one of each logical output from said step of masking with said complementary mask.

A data processing system for generating partial logical shifts of a logical comprising:

• an instruction dispatch device adapted for retrieving instructions from an instruction storage device;
• a partial logical shift device coupled to said instruction dispatch device, and generating a partially shifted output signal from the logical signal received from said dispatch device in response to instructions therefrom, said shift device comprising:
• a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of said logic signal;
• and
• a plurality of logic circuits, each logic circuit having a first input couple to an output of a first predetermined barrel shifter, and a second input coupled to an output of a second predetermined barrel shifter, wherein each said logic circuit outputs a portion of said partially shifted output signal, said output of each logic circuit being a logical combination formed in response to said first and second inputs, wherein said plurality of said logics includes a first subset of logic circuits having a third input coupled to an output of a third predetermined barrel shifter.

A data processing system for generating partial logical shifts of a logical comprising:

• an instruction dispatch device adapted for retrieving instructions from an instruction storage device;
• a partial logical shift device coupled to said instruction dispatch device, and generating a partially shifted output signal from the logical signal received from said dispatch device in response to instructions therefrom, said shift device comprising:
• a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of said logic signal;
• and
• a plurality of logic circuits, each logic circuit having a first input couple to an output of a first predetermined barrel shifter, and a second input coupled to an output of a second predetermined barrel shifter, wherein each said logic circuit outputs a portion of said partially shifted output signal, said output of each logic circuit being a logical combination formed in response to said first and second inputs, wherein each logic circuit of said plurality of logic circuits includes a third input adapted for receiving a mass signal, and wherein each logic circuit includes an inverter having an input comprising said third input, said inverter outputting a complimentary mask signal, said output of said logic circuit including a portion formed in response to said complementary mask signal.

A data processing system for generating partial logical shifts of a logical comprising:

• an instruction dispatch device adapted for retrieving instructions from an instruction storage device;
• a partial logical shift device coupled to said instruction dispatch device, and generating a partially shifted output signal from the logical signal received from said dispatch device in response to instructions therefrom, said shift device comprising:
• a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of said logic signal;
• and
• a plurality of logic circuits, each logic circuit having a first input couple to an output of a first predetermined barrel shifter, and a second input coupled to an output of a second predetermined barrel shifter, wherein each said logic circuit outputs a portion of said partially shifted output signal, said output of each logic circuit being a logical combination formed in response to said first and second inputs, wherein each logic circuit of said plurality of logic circuits includes a third input adapted for receiving a mass signal, and wherein each logic includes an AND gate, said AND gate having a first input comprising said logic circuit first input, and the second input comprising said logic circuit third input, said AND gate outputting a portion of said output of each logic circuit.

A data processing system for generating partial logical shifts of a logical comprising:

• an instruction dispatch device adapted for retrieving instructions from an instruction storage device;
• a partial logical shift device coupled to said instruction dispatch device, and generating a partially shifted output signal from the logical signal received from said dispatch device in response to instructions therefrom, said shift device comprising:
• a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of said logic signal;
• and
• a plurality of logic circuits, each logic circuit having a first input couple to an output of a first predetermined barrel shifter, and a second input coupled to an output of a second predetermined barrel shifter, wherein each said logic circuit outputs a portion of said partially shifted output signal, said output of each logic circuit being a logical combination formed in response to said first and second inputs, wherein said plurality of said logic circuits includes a first subset of logic circuits, said first subset including logic circuits wherein said second predetermined barrel shifter is a barrel shifter succeeding said first predetermined barrel shifter, and wherein said partial logical shift device is adapted for receiving a mass signal, and wherein each logic circuit of said first subset comprises an AND gate, said AND gate having a first input coupled to said barrel shifter preceding said first predetermined barrel shifter and a second input adapted for receiving a complimentary mask signal generated in response to said mask signal, an output of said AND gate forming a portion of said output of each logic circuit.

A data processing system for generating partial logical shifts of a logical comprising:

• an instruction dispatch device adapted for retrieving instructions from an instruction storage device;
• a partial logical shift device coupled to said instruction dispatch device, and generating a partially shifted output signal from the logical signal received from said dispatch device in response to instructions therefrom, said shift device comprising:
• a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of said logic signal;
• and
• a plurality of logic circuits, each logic circuit having a first input couple to an output of a first predetermined barrel shifter, and a second input coupled to an output of a second predetermined barrel shifter, wherein each said logic circuit outputs a portion of said partially shifted output signal, said output of each logic circuit being a logical combination formed in response to said first and second inputs, wherein said plurality of said logic circuits includes a first subset of logic circuits, said first subset including logic circuits wherein said second predetermined barrel shifter is a barrel shifter preceding said first predetermined barrel shifter, and wherein said partial logical shift device is adapted for receiving a mask signal, and wherein each logic circuit of said first subset comprises an AND gate, said AND gate having a first input coupled to said barrel shifter succeeding said first predetermined barrel shifter and a second input adapted for receiving a complimentary mask signal generated in response to said mask signal, an output of said AND gate forming a portion of said output of each logic circuit.

An apparatus for generating partial logical shifts of a logical signal comprising:

• a first barrel shifter having an input adapted for receiving a first portion of said logical signal;
• a second barrel shifter having an input adapted for receiving a second portion of said logical signal;
• a third barrel shifter having an input adapted for receiving a third portion of said logical signal;
• a fourth barrel shifter having an input adapted for receiving a fourth portion of said logical signal;
• a first logic circuit coupled to an output of said first barrel shifter, said first logic circuit comprising:
• a first AND gate having a first input coupled to said first barrel shifter, and a second input adapted for receiving a mask signal;
• a first inverter having an input adapted for receiving said mask signal, said inverter outputting a complementary mask signal;
• a second AND gate having first input coupled to an output of said first inverter, and a second input coupled to an output of said second barrel shifter;
• a first multiplexer (MUX) having a first input coupled to an output of said second AND gate, a second input receiving a plurality of bits all of which have the value zero, and a third input adapted for receiving a control signal, said first MUX selecting a signal for outputting in response thereto;
• and
• a first OR gate having a first input coupled to an output of said first AND gate, and a second input coupled to an output of said first MUX, said OR gate outputting a first portion of an output signal;
• a second logic circuit coupled to said output of said second barrel shifter, said second logic circuit comprising:
• a third AND gate having a first input coupled to said second barrel shifter, and a second input adapted for receiving said mask signal;
• a second inverter having an input adapted for receiving said mask signal, said inverter outputting a complementary mask signal;
• a fourth AND gate having first input coupled to an output of said second inverter, and a second input coupled to an output of said third barrel shifter;
• a fifth AND gate having a first input coupled to said output of said second inverter, and a second input coupled to said output of said first barrel shifter;
• a second multiplexer (MUX) having a first input coupled to an output of said fourth AND gate, a second input coupled to an output of said fifth AND gate, and a third input adapted for receiving said control signal, said second MUX selecting a signal for outputting in response thereto;
• and
• a second OR gate having a first input coupled to an output of said third AND gate, and a second input coupled to an output of said second MUX, said OR gate outputting a second portion of said output signal;
• a third logic circuit coupled to said output of said third barrel shifter, said second logic circuit comprising:
• a sixth AND gate having a first input coupled to said third barrel shifter, and a second input adapted for receiving said mask signal;
• a third inverter having an input adapted for receiving said mask signal, said inverter outputting a complementary mask signal;
• a seventh AND gate having first input coupled to an output of said third inverter, and a second input coupled to an output of said second barrel shifter;
• a eighth AND gate having a first input coupled to said output of said third inverter, and a second input coupled to said output of said fourth barrel shifter;
• a third multiplexer (MUX) having a first input coupled to an output of said seventh AND gate, a second input coupled to an output of said eighth AND gate, and a third input adapted for receiving said control signal, said third MUX selecting a signal for outputting in response thereto;
• and
• a third OR gate having a first input coupled to an output of said sixth AND gate, and a second input coupled to an output of said third MUX, said OR gate outputting a third portion of said output signal;
• and
• a fourth logic circuit coupled to an output of said fourth barrel shifter, said fourth logic circuit comprising:
• a ninth AND gate having a first input coupled to said fourth barrel shifter, and a second input adapted for receiving said mask signal;
• a fourth inverter having an input adapted for receiving said mask signal, said inverter outputting a complementary mask signal;
• a tenth AND gate having first input coupled to an output of said fourth inverter, and a second input coupled to an output of said third barrel shifter;
• a fourth multiplexer (MUX) having a first input coupled to an output of said tenth AND gate, a second input receiving a plurality of bits all of which have the value zero, and a third input adapted for receiving said control signal, said fourth MUX selecting a signal for outputting in response thereto;
• and
• a fourth OR gate having a first input coupled to an output of said ninth AND gate, and a second input coupled to an output of said fourth MUX, said OR gate outputting a fourth portion of said output signal.