Layout input apparatus, layout input method, layout verification apparatus, and layout verification method

A layout input method, comprising the steps of:

• inputting first coordinate information representing a position of a first circuit portion included in a first semiconductor integrated circuit and second coordinate information representing a position of a second circuit portion included in a second semiconductor integrated circuit;
• performing a predetermined coordinate transformation with respect to the second coordinate information;
• storing the first coordinate information as at least a part of first layout data representing a layout of the first semiconductor integrated circuit and storing the transformed second coordinate information as at least a part of second layout data representing a layout of the second semiconductor integrated circuit;
• and
• displaying the first and the second coordinate information so as to overlap at least partially;
• wherein the first semiconductor integrated circuit is formed on a first surface of a first semiconductor chip;
• the second semiconductor integrated circuit is formed on a second surface of a second semiconductor chip;
• the first semiconductor chip and the second semiconductor chip are mounted so as to overlap in such a manner so that the first surface and the second surface are formed to face each other;
• and
• wherein the first coordinate information and the transformed second coordinate information are transferred to a storage section for carrying out the storing step;
• and
• the first coordinate information and the second coordinate information are transferred to a display section for carrying out the displaying step.

A layout verification apparatus, comprising:

• a storage section for storing first layout data representing a layout of a first semiconductor integrated circuit, second layout data representing a layout of a second semiconductor integrated circuit which is different from the first semiconductor integrated circuit, and connection information defining a position of a connection portion connecting the first semiconductor integrated circuit to the second semiconductor integrated circuit;
• and
• a control section for specifying a first position in the first layout data corresponding to the position of the connection portion and a second position in the second layout data corresponding to the position of the connecting portion, based on the connection information, and verifying the layouts of the first and second semiconductor integrated circuits, considering that the first position is connected to the second position,
• wherein the first and second semiconductor integrated circuits are separately formed on discrete substrates.

A layout verification method verifying layouts of first and second semiconductor integrated circuits, based on first layout data representing the layout of a first semiconductor integrated circuit, second layout data representing the layout of a second semiconductor integrated circuit which is different from the first semiconductor integrated circuit, and connection information defining a position of a connecting portion connecting the first semiconductor integrated circuit to the second semiconductor integrated circuit, comprising the steps of:

• a) specifying a first position in the first layout data corresponding to the position of the connecting portion and a second position of the second layout data corresponding to the position of the connecting portion, based on the connection information;
• and
• b) verifying the layouts of the first and second semiconductor integrated circuits, considering that the first position is connected to the second position,
• wherein the first and second semiconductor integrated circuits are separately formed on discrete substrates.