Fractional-spurs suppression scheme in frequency tracking multi-band fractional-N phase lock loop
AssigneeTexas Instruments Incorporated
InventorsAbdellatif Bellaouar, Khaled M. Sharaf, Ahmed Reda Fridi
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Abstract
The present invention discusses fractional compensation timing circuitry (15) to track a VCO output frequency, fO, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.
Claims18
A phase-lock-loop circuit, comprising:
- an oscillator;
- a phase detector;
- a filter circuit;
- a first divider circuit;
- a digital to analog converter;
- a second divider circuit coupling said oscillator to said phase detector;
- a charge pump coupling said phase detector to said filter circuit;
- a voltage controlled oscillator coupling said filter circuit to said first divider circuit;
- an L-Bit accumulator coupling said first divider circuit to said digital-to-analog converter;
- a fractional charge pump coupling said digital-to-analog converter to said charge pump and to said filter circuit;
- and
- a fractional timing circuit coupling said voltage controlled oscillator and said first divider circuit to said phase detector and to said fractional charge pump.
A phase-lock-loop circuit, comprising circuitry for generating a precise fractional pulse width signal having voltage controlled oscillator tracking characteristics, said circuit further including circuitry, coupling an output of said phase-lock-loop to an input of a phase detector within said phase-lock-loop, for:
- tracking variations in the output frequency (fO) of the phase-lock-loop circuit at the output of a voltage controlled oscillator within said phase-lock-loop;
- developing compensation current that is independent of voltage controlled oscillator frequency;
- and developing a pulse-amplitude-modulated fractional compensation pulse having a width that tracks the voltage controlled oscillator frequency.
A phase-lock-loop circuit, comprising circuitry for generating a precise fractional pulse width signal having voltage controlled oscillator tracking characteristics, said circuit further including fractional pulse timing circuitry, coupling an output of said phase-lock-loop to an input of a phase detector within said phase-lock-loop, for tracking the output frequency (fO) and circuitry responsive to said fractional pulse timing circuitry for providing effective error cancellation in said phase-lock-loop;
- circuitry for tracking the output frequency (fO) and circuitry responsive to said fractional pulse timing circuitry for providing effective error cancellation in said phase-lock-loop;
- and
- circuitry for developing compensation current that is independent of voltage controlled oscillator frequency;
- and developing a pulse-amplitude-modulated fractional compensation pulse having a width that tracks the voltage controlled oscillator frequency.
A method for tracking the output frequency (fO) of a phase-lock-loop synthesizer and providing effective error cancellation in said phase-lock-loop, comprising the steps of:
- tracking band changes in the output frequency of a voltage controlled oscillator within said phase-lock-loop;
- developing compensation current that is independent of voltage controlled oscillator frequency;
- and developing a pulse-amplitude-modulated fractional compensation pulse having a width that tracks the voltage controlled oscillator frequency.
A wireless telephonic system, comprising:
- a duplex switch coupling an antenna to a receiver and to a transmitter;
- a power supply coupled to said receiver;
- a baseband coupling aid power supply to said receiver, transmitter and to a keypad and a speaker;
- a microphone coupled to said baseband;
- and
- a phase-lock-loop circuit coupling said receiver to said transmitter, said phase-lock-loop including circuitry for tracking variations in the output frequency (fO) of the phase-lock-loop circuit at the output of a voltage controlled oscillator within said phase-lock-loop, including fractional timing circuitry for tracking the output frequency (fO) and circuitry responsive to said fractional timing circuitry for providing effective error cancellation in said phase-lock-loop, said fractional timing circuit comprising synchronization circuitry, control logic circuitry and divide by circuitry coupling said synchronization circuitry to said control logic circuitry and wherein:
- a first output of said synchronization circuitry is coupled to said second input of said phase detector;
- a second output of said synchronization is coupled to a first input of said divide by circuit;
- a first output of said divide by circuitry is coupled to an input of said fractional charge pump;
- a second output of said divide by circuit is coupled to a first input of said control logic circuitry;
- an output of said control logic circuitry is coupled to a second input of said divide by circuitry;
- an output of said first divider circuitry is coupled to a first input of said synchronization circuitry and to a second input of said control logic circuitry;
- and
- an output of said voltage controlled oscillator is coupled to a third input of said divide by circuitry.
Dependencies are inferred from the claim text.