Switching noise reduction in a multi-clock domain transceiver

A method for reducing system performance degradation due to switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the sampling clock signals being synchronous in frequency, the digital sections operating in accordance with a receive clock signal, the method comprising:

• generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals;
• adjusting the phase offset such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized;
• wherein adjusting the phase offset of the receive clock comprises:
• (1) determining a set of phase offset values for the phase offset;
• (2) computing a set of system performance errors corresponding one-to-one to the phase offset values;
• and
• (3) selecting one of the phase offset values, said one phase offset value corresponding to a minimum of the system performance errors.

A method for reducing system performance degradation due to switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the sampling clock signals being synchronous in frequency, the digital sections operating in accordance with a receive clock signal, the method comprising:

• generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals;
• adjusting the phase offset such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized;
• adjusting a sampling phase of at least one of the sampling clock signals such that a subsystem performance error of the subsystem which corresponds to said one of the sampling clock signals is substantially minimized;
• wherein adjusting the sampling phase of at least one of the sampling clock signals comprises:
• (1) determining a set of sampling phase values for the sampling phase;
• (2) computing a set of subsystem performance errors corresponding one-to-one to the sampling phase values;
• and
• (3) selecting one of the sampling phase values, said one sampling phase value corresponding to a minimum of the subsystem performance errors.

A method for reducing effect of switching noise in a system, the system comprising a set of subsystems, each of the subsystems comprising an analog section and a digital section, each of the analog sections operating in accordance with a corresponding one of a set of sampling clock signals, the digital sections operating in accordance with a receive clock signal, the method comprising:

• generating the sampling clock signals such that the sampling clock signals are synchronous in frequency with each other;
• generating the receive clock signal such that the receive clock signal is synchronous in frequency with the sampling clock signals and having a phase offset with respect to one of the sampling clock signals;
• adjusting the phase offset such that effect of switching noise from the digital sections on the analog sections is substantially minimized;
• wherein, in adjusting the phase offset, the phase offset is adjusted such that time difference between a transition occurrence of the receive clock signal and transition occurrences of sampling clock signals that are adjacent in time to the transition occurrence of the receive clock signal is substantially maximized.