Clock recovery circuit
AssigneeMotorola, Inc.
InventorsShih Sheng Hu, Chien Yu Lai
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Abstract
An edge detector (10) detects edges of clock pulses in a digital signal and provides edge detect pulses to a state corrector (20). A state sequencer (15) receives a clock signal and steps through a sequence of states in accordance with the clock signal to generate a recovered clock signal which is substantially synchronized with the clock pulses in the digital signal. The state corrector (20) selectively providing reset states to reset the state sequencer in accordance with various parameters to maintain synchronization between the clock pulses in the digital signal and the recovered clock signal. The state corrector (20) also inhibits resetting the state sequencer (15) when edge detect pulse produced from instability in the edge detector (10) are received.
Claims19
A clock recovery circuit comprising:
- a clock information edge detector comprising:
- a digital signal input;
- and
- an edge detect signal output;
- a state sequencer comprising:
- a clock signal input;
- a current state signal output;
- a state reset signal input;
- and
- a recovered clock information signal output;
- and
- a state corrector comprising:
- an edge detect signal input coupled to the edge detect signal output of the clock information edge detector;
- a current state signal input coupled to the current state signal output of the state sequencer;
- and
- a state reset signal output coupled to the state reset signal input of the state sequencer.
A clock recovery circuit comprising:
- an edge detector means having an input for receiving a digital signal which includes clock information edges and an output for providing a detect signal indicative of detection of the clock information edges in the digital signal;
- a state sequencer means having a first input for receiving a clock signal having a frequency that is greater than that of the digital signal by a factor N, for stepping through a predetermined sequence of N states in accordance with the clock signal, the state sequencer means having a first output for providing a current state signal indicating a current state, a second input for receiving a state reset signal indicating a reset state, and a second output for providing a recovered clock information signal in accordance with at least part of the current state signal;
- and
- a state corrector means having a first input coupled to the output of the edge detector means for receiving the edge detect signal, a second input coupled to the first output of the state sequencer means to receive the current state signal, the state corrector means for determining whether the current state is one of a plurality of predetermined resettable states, and a second output coupled to the second input of the state sequencer means to provide the state reset signal, wherein the state corrector means includes a state counter means for counting the number of states between subsequent clock information edges,
- and when at least one clock information edge is detected and the current state is one of the plurality of predetermined resettable states, the state corrector means being adapted to provide the state reset signal indicating:
- an earlier state than the current state when the state counter means value is greater than N;
- and
- a later state than the current state when the state counter means value is less than N.
A method for recovering a clock signal comprising the steps of:
- a) receiving a clock signal and a digital signal which includes clock information edges, wherein the clock signal has an integral multiple N higher frequency than that of the digital signal;
- b) stepping through a predetermined sequence of N states in accordance with the clock signal;
- c) providing a current state signal indicating a current state;
- d) detecting a clock information edge in the digital signal;
- e) counting the number of states since the detection of the last clock information edge;
- f) determining whether the current state is one of a plurality of predetermined allowable states;
- g) comparing the number of states counted with N;
- h) resetting a state sequencer to an earlier state than the current state when the number of states counted is greater than N;
- i) resetting the state sequencer to a later state than the current state when the number of states counted is less than N;
- and
- j) generating a recovered clock information signal in accordance with at least part of the current state signal.
Dependencies are inferred from the claim text.