ATM cell transmission system

An ATM cell transmission system having an ATM layer device, a data path interface and a plurality of normal PHY layer devices whereof each is connected to the ATM layer device by way of the data path interface and returns a HIGH level of a cell transmission allowance signal on condition said each can accept one more whole ATM cell when said each is polled by the ATM layer device through the data path interface;

• said ATM layer device comprising:
• a cell buffer for storing ATM cells to be transmitted through the normal PHY layer devices;
• FIFO memories each provided corresponding to each one of the normal PHY layer devices;
• a transmission cell selector for selecting one of the FIFO memories as a next sender for transmitting cell data through the data path interface at a next cell transmission cycle following a current cell transmission cycle;
• and
• a cell transmission controller for
• performing polling of the normal PHY layer devices,
• designating a selected PHY layer device among the normal PHY layer devices which have returned the HIGH level of the cell transmission allowance signal to the polling and satisfy either of a first condition that at least one ATM cell to be forwarded thereto is stored in the cell buffer and a second condition that corresponding FIFO memories are not empty,
• controlling the cell buffer to output an ATM cell to be transmitted through the selected PHY layer device into one of the FIFO memories corresponding to the selected PHY layer device on condition that the ATM cell is stored in the cell buffer,
• controlling the transmission cell selector to select said one of the FIFO memories as the next sender, and
• designating the selected PHY layer device at an end of the current transmission cycle as a next receiver of the cell data to be transmitted through the data path interface at the next cell transmission cycle.

An ATM cell transmission system having an ATM layer device, a data path interface and a plurality of enhanced PHY layer devices whereof each is connected to the ATM layer device by way of the data path interface and returns a HIGH level of a cell transmission allowance signal on condition said each can accept K more whole ATM cells when said each is polled by the ATM layer device through the data path interface, K being an integer more than one;

• said ATM layer device comprising:
• a cell buffer for storing ATM cells to be transmitted through the enhanced PHY layer devices;
• a FIFO memory;
• a cell transmission controller for
• performing polling of the normal PHY layer devices,
• designating a selected PHY layer device among the enhanced PHY layer devices which have returned the HIGH level of the cell transmission allowance signal to the polling and satisfy a condition that at least one ATM cell to be forwarded thereto is stored in the cell buffer,
• controlling the cell buffer to output an ATM cell to be transmitted through the selected PHY layer device into the FIFO memory together with destination information of the ATM cell,
• controlling the FIFO memory to transmit cell data of an ATM cell through the data path at a next cell transmission cycle when the FIFO memory is not empty, and
• designating an enhanced PHY layer device indicated by the destination information of the ATM cell at an end of the current transmission cycle as a next receiver of the cell data to be transmitted through the data path interface at the next cell transmission cycle.

An ATM cell transmission system having an ATM layer device, a data path interface and a plurality of PHY layer devices whereof each is connected to the ATM layer device by way of the data path interface, and each is either one of a normal PHY layer device which returns a HIGH level of a cell transmission allowance signal on condition said each can accept one more whole ATM cell when said each is polled by the ATM layer device through the data path interface and an enhanced PHY layer device which returns the HIGH level of the cell transmission allowance signal on condition said each can accept K more whole ATM cells when said each is polled by the ATM layer device through the data path interface, K being an integer more than one;

• said ATM layer device comprising:
• a cell buffer for storing ATM cells to be transmitted through the PHY layer devices;
• a FIFO memory;
• a cell transmission controller for
• performing polling of the PHY layer devices,
• designating a selected PHY layer device among the PHY layer devices which have returned the HIGH level of the cell transmission allowance signal to the polling and satisfy a first condition that at least one ATM cell to be forwarded thereto is stored in the cell buffer and a second condition that addresses thereof are not registered as one of D selected port numbers, D being a number of cell transmission cycles needed for outputting an ATM cell from the cell buffer to the FIFO memory according to the polling after the polling is performed,
• controlling the cell buffer to output an ATM cell to be transmitted through the selected PHY layer device into the FIFO memory together with destination information of the ATM cell,
• replacing one of the D selected port numbers which is registered earliest with an address of the selected PHY layer device when the selected PHY layer device is the normal PHY layer device and with an invalid address when the selected PHY layer device is the enhanced PHY layer device,
• controlling the FIFO memory to transmit cell data of an ATM cell through the data path at a next cell transmission cycle when the FIFO memory is not empty, and
• designating a PHY layer device indicated by the destination information of the ATM cell at an end of the current transmission cycle as a next receiver of the cell data to be transmitted through the data path interface at the next cell transmission cycle.