Asynchronous transfer mode controller and ATM control method thereof and ATM communication control apparatus

An ATM controller connected between an ATM network data transmission path and a terminal for performing processing of an ATM layer and an ATM Adaptation Layer of an ATM protocol used, said controller comprising:

• a transfer circuit, connected with a buffer memory which stores packet data with at least one de-assembled predetermined length data block, for transferring the data packet according to the extent of the predetermined length data block between said buffer memory and a memory in said terminal;
• a cell transmit control circuit de-assembling the predetermined data block sent from said terminal memory to said buffer memory into a data cell and the packet data sent from said terminal memory into a data cell, for transmitting one of the data cells to the ATM network;
• a cell receive control circuit for re-assembling a data cell received from said ATM network into at least one predetermined length data block and store in the buffer memory, and from packet data from the received data cell on said terminal memory received data cell;
• and
• a transfer control circuit for instructing said transfer circuit to transfer the predetermined data block between said buffer memory and said terminal memory, and instructing said cell transmit control circuit and said cell receive control circuit to transfer the data cell between one of selected from said buffer memory and said terminal memory and said ATM network through the transmission path.

ATM communication control apparatus adapted to be connected between a transfer path of an ATM network and a terminal for execution of processing of an ATM Layer and ATM Adaptation Layer (AAL) plus Physical (PHY) layer of an ATM protocol, said apparatus comprising:

• an ATM controller including a buffer memory, a transfer circuit for transfer of packet data between said buffer memory and an internal memory of said terminal with a predetermined length data block being a unit therefor, cell transmit control circuit for sub-dividing said predetermined length data block sent from the internal terminal memory to said buffer memory into data cells for transmission to the ATM network, cell receive control circuit for reconstruction of the data cells received from said ATM network over said transfer path to form in said buffer memory a predetermined length data block, and a transfer control circuit for instructing said transfer circuit to transfer said predetermined length data block between said buffer memory and said internal terminal memory and for instructing said cell transmit control circuit and said cell receive control circuit to transfer said data cell between said buffer memory and said ATM network via said transfer path;
• a PHY controller as connected between said ATM controller and said transfer path for executing processing of the PHY layer;
• and
• a quartz oscillator for use in driving said PHY controller.

ATM communication control apparatus adapted to be connected between a transfer path of an ATM network and a terminal for performing processing of an ATM Layer and AAL Layer plus PHY Layer of an ATM protocol, said apparatus comprising:

• a buffer memory;
• an ATM controller including a transfer circuit for transfer of packet data between said buffer memory and an internal memory of said terminal with a predetermined length data block being a unit therefor, cell transmit control circuit for subdividing one of said predetermined length data block transferred from the internal terminal memory to said buffer memory and said packet data from said internal terminal memory into data cells for transmission to the ATM network, cell receive control circuit for performing one of reassembly of the data cells received from said ATM network over said transfer path for formation of a predetermined length data block in said buffer memory and formation of the received data cells into more than one packet data in said terminal memory, and a transfer control circuit for instructing said transfer circuit to transfer said predetermined length data block between said buffer memory and said terminal memory and instructing said cell transmit control circuit and said cell receive control circuit to transfer said data cells between one of said buffer memory and said terminal memory and said ATM network via said transfer path;
• a PHY controller connected between said ATM controller and said transfer path for executing a processing of said PHY layer;
• and
• a quartz oscillator for use in driving said PHY controller.

A method for controlling an ATM controller connected between a transfer path of an ATM network and a terminal for performing processing of an ATM layer and an AAL layer of an ATM protocol, said method comprising the steps of:

• transferring a data packet to an extent of a predetermined length data block between a buffer memory and an internal memory of said terminal;
• de-assembling said predetermined length data block, sent from said internal memory to said buffer memory which stores packet data with at least one de-assembled predetermined length data block, into data cells to be transmitted to the ATM network;
• and
• assembling data cells received from said ATM network via said transfer path to form a predetermined length data block in said buffer memory.