Semiconductor memory device capable of efficient memory cell select operation with reduced element count
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
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Abstract
Four subordinate word lines are driven for a single main word line. In a subordinate word driver circuit, a bank select line activated allows a potential level of a main word line to be transmitted to an internal node via a first transistor. Simultaneously, a select line is also active and a potential level of the internal node is transmitted to a subordinate word line via a second transistor. A bank select line is inactivated and the select line is then further boosted to a boosted potential so that it is driven to a boosted potential of a potential level of the subordinate word line.
Claims6
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns, and divided into a plurality of memory cell blocks in rows and columns;
- a row select circuit provided for said memory cell array, selecting said memory cell row in response to an address signal;
- a block select circuit indicating a selected memory cell block in response to said address signal;
- a plurality of redundant memory cell blocks provided independently of said memory cell blocks;
- and
- a redundancy determination circuit previously storing a memory cell block address having a defective memory cell to select a redundant memory cell in said redundant memory cell block when a memory cell designated by an address signal corresponds to said defective memory cell.
Dependencies are inferred from the claim text.