Trimming circuit for system integrated circuit
AssigneeFujitsu Limited
InventorsYasushige Ogawa, Eisaku Itoh, Yoshiyuki Ishida
Life of this patent
Estimating the term…
Abstract
A system LSI circuit which includes multiple memory circuits and functional logic circuits includes a control circuit for controlling the voltage supplied to the memory circuits. The control circuit includes trimming circuits for adjusting the memory supply voltages to ensure that the supplied voltages are within predetermined tolerances. The control circuit services all of the memory circuits, such that redundant logic functions are consolidated and multiple pads are not required to measure the memory supply voltages.
Claims21
A semiconductor integrated circuit comprising:
- a plurality of memory units;
- and
- a reference potential control circuit connected to the plurality of memory units to control a reference potential at each of the memory units, wherein the reference potential control circuit includes a trimming circuit for performing a trimming process and generating a predetermined potential in order to generate the reference potential within a predetermined range.
A method for designing a semiconductor integrated circuit comprising the steps of:
- preparing data for a control macro used to control a reference potential at each of a plurality of memory units;
- preparing data of each of the memory units;
- laying out each of the memory units and the control macro on a chip using the data of each of the memory units and the data of the control macro;
- and
- connecting each of the memory units and the control macro,
- wherein the data of the control macro includes the data of a trimming circuit for performing a trimming process and generating a predetermined potential in order to generate the reference potential within a predetermined range.
A computer readable recording medium which includes program code for generating layout data of a semiconductor integrated circuit, the program code performing the steps of:
- preparing data of a control macro used to control a reference potential at each of a plurality of memory units;
- preparing data of each of the memory units;
- laying out each of the memory units and the control macro on a chip using the data of each of the memory units and the data of the control macro;
- connecting each of the memory units and the control macro,
- wherein the data of the control macro includes the data of a trimming circuit for performing a trimming process and generating a predetermined potential in order to generate the reference potential within a predetermined range.
Dependencies are inferred from the claim text.