Reading device for integrated circuit memory
AssigneeSTMicroelectronics S.r.l.
InventorsRichard Fournel, Laura Varisco
Life of this patent
Estimating the term…
Abstract
A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.
Claims35
A reading device for an integrated circuit memory comprising:
- a first current-to-voltage converter having an input connected by a data bit line to a memory cell, said first current-to-voltage converter precharging the data bit line to a first precharging voltage in a precharging phase;
- a second current-to-voltage converter having an input connected by a reference bit line to a reference cell, the second current-to-voltage converter precharging the reference bit line to the first precharging voltage in the precharging phase;
- a differential amplifier having a first input connected to an output of the first current-to-voltage converter and a second input connected to an output of the second current-to-voltage converter;
- a read current generator for providing a current on each of said data bit and reference bit lines and enabling data to be provided at an output of the reading device in an evaluation phase;
- and
- a charging circuit for precharging the first and second inputs of the differential amplifier to a second precharging voltage between the first precharging voltage and a supply voltage during the precharging phase.
A reading device for an integrated circuit memory comprising:
- a first precharge circuit having an input connected to a data bit line and precharging the data bit line to a first precharging voltage in a precharging phase;
- a second precharge circuit having an input connected to a reference bit line and precharging the reference bit line to the first precharging voltage in the precharging phase;
- a differential amplifier having a first input connected to an output of the first precharge circuit and a second input connected to an output of the second precharge circuit;
- a read current generator for providing a current on each of said data bit and reference bit lines and enabling data to be provided at an output of the reading device in an evaluation phase;
- and
- a charging circuit for precharging the first and second inputs of the differential amplifier to a second precharging voltage different that the first precharging voltage during the precharging phase.
An integrated circuit memory comprising:
- a memory cell;
- a reference cell;
- a reading device comprising
- a first precharge circuit having an input connected by a data bit line to said memory cell, said first precharge circuit precharging the data bit line to a first precharging voltage in a precharging phase,
- a second precharge circuit having an input connected by a reference bit line to said reference cell, the second precharge circuit precharging the reference bit line to the first precharging voltage in the precharging phase,
- a differential amplifier having a first input connected to an output of the first precharge circuit and a second input connected to an output of the second precharge circuit,
- a read current generator for providing a current on each of said data bit and reference bit lines and enabling data to be provided at an output of the reading device in an evaluation phase, and
- a charging circuit for precharging the first and second inputs of the differential amplifier to a second precharging voltage different that the first precharging voltage during the precharging phase.
A method for reading data from an integrated circuit memory comprising:
- precharging a data bit line connected to an input of a first precharge circuit to a first precharging voltage in a precharging phase;
- precharging a reference bit line connected to an input of a second precharge circuit to the first precharging voltage in the precharging phase;
- providing a current on each of the data bit and reference bit lines to enable the data to be provided in an evaluation phase;
- and
- precharging first and second inputs of a differential amplifier to a second precharging voltage during the precharging phase, the first input of the differential amplifier being connected to an output of the first precharge circuit and the second input of the differential amplifier being connected to an output of the second precharge circuit.
Dependencies are inferred from the claim text.