Dynamic random access memory

A semiconductor memory device, comprising:

• dynamic memory cells arranged in a row and column array, each of said dynamic memory cells comprising a transfer MOS transistor of a first conductivity type and a capacitive element coupled to said transfer MOS transistor for storing data;
• word lines each connecting the dynamic memory cells in one row of said array;
• bit lines each connecting the dynamic memory cells in one column of said array;
• pads to which receiving external address signals are applied;
• address amplifying circuits responsive to the external address signals applied to the pads for generating first internal address signals selecting a first number of said word lines in a normal operation mode;
• a word line driving voltage source;
• word line selecting circuits responsive to the first internal address signals for outputting word line selecting signals, said word line selecting circuits each comprising a logic gate for decoding the first internal address signals and a precharge transistor having a first current terminal coupled to said word line driving voltage source, a second current terminal coupled to an output of said logic gate, and a control terminal receiving a precharge signal for precharging the output of said logic gate;
• a control circuit responsive to a voltage stress test control signal for selecting a second number of said word lines in a voltage stress test operation mode, the second number being greater than the first number;
• and
• word line driving circuits coupled between corresponding ones of said word line selecting circuits and said word line, said word line driving circuits having first and second transistors, the first transistor of a second conductivity type having a first current terminal to which a voltage from said word line driving voltage source is applied, a second current terminal coupled to the corresponding one of said word lines, and a control terminal coupled to the corresponding one of said word line selecting circuits, and the second transistor of the first conductivity type having a first current terminal coupled to the corresponding one of said word lines, a second current terminal coupled to the ground potential, and a control terminal coupled to the corresponding one of said word line selecting circuits.