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US 6,307,795 B1Granted
Semiconductor memory having multiple redundant columns with offset segmentation boundaries
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
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Abstract
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5>and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.
Claims31
A memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- a plurality of row lines for accessing memory cells in respective rows of said first bank based on a row address, said plurality of row lines being divided into a plurality of row blocks, each row block containing a respective plurality of row lines;
- a plurality of row decoders respectively coupled to said blocks of row lines for selectively activating an addressed row line;
- a plurality of column lines, each of said plurality of column lines being used to access memory cells in a respective column of said first bank;
- at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells;
- and
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells, at least some of said segments of said at least one second redundant column having boundaries that are offset from boundaries of said segments of said at least one first redundant column.
4 more elements
A memory device comprising:
- a first bank of memory cells arranged in row and columns, said first bank of memory cells including primary columns of memory cells and at least one first and at least one second redundant column of memory cells used for repairing out defective memory cells in said primary columns;
- at least one first redundant column line for accessing memory cells in said at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a primary column of said first bank, said at least one first redundant column being divided into a plurality of column segments;
- and
- at least one second redundant column line for accessing memory cells in said at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a primary column of said first bank, said at least one second redundant column being divided into a plurality of column segments, at least some of said segments of said at least one second redundant column being offset with respect to at least some of said segments of said at least one first redundant column.
1 more element
A memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- and
- a first redundant column of said first bank, said first redundant column being divided into a plurality of column segments;
- and
- a second redundant column of said first bank, said second redundant column being divided into a plurality of segments, at least one of said plurality of segments of said second redundant column being programmably misaligned to at least one of said segments of said first redundant column.
2 more elements
A processor system comprising:
- a central processing unit;
- and
- a memory device connected to said processing unit;
- said memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- a plurality of row lines for accessing memory cells in respective rows of said first bank based on a row address, said plurality of row lines being divided into a plurality of row blocks, each row block containing a respective plurality of row lines;
- a plurality of row decoders respectively coupled to said blocks of row lines for selectively activating an addressed row line;
- a plurality of column lines, each of said plurality of column lines being used to access memory cells in a respective column of said first bank;
- at least one first redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells;
- and
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least one second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, each of said column segments spanning at least two blocks of rows of said first bank of memory cells, at least some of said segments of said at least one second redundant column having boundaries that are offset from boundaries of said segments of said at least one first redundant column.
8 more elements
A processor system comprising:
- a central processing unit;
- and
- a memory device connected to said processing unit;
- said memory device comprising:
- a first bank of memory cells arranged in rows and columns,
- at least one firs t redundant column line for accessing memory cells in at least one first redundant column of said first bank, said at least one first redundant column being used to repair out defective memory cells in a column of said first bank, said at least one first redundant column being divided into a plurality of column segments;
- and
- at least one second redundant column line for accessing memory cells in at least one second redundant column of said first bank, said at least on e second redundant column being used to repair out defective memory cells in a column of said first bank, said at least one second redundant column being divided into a plurality of column segments, at least some of said segments of said at least one second redundant column being offset with respect to at least some of said segments of said at least one first redundant column.
5 more elements
A processor system comprising:
- a central processing unit;
- and
- a memory device connected to said processing unit;
- said memory device comprising:
- a first bank of memory cells arranged in rows and columns;
- a first redundant column of said first bank, said first redundant column being divided into a plurality of column segments;
- and
- a second redundant column of said first bank, said second redundant column being divided into a plurality of segments, at least one of said plurality of segments of said second redundant column being programmably misaligned to at least one of said segments of said first redundant column.
5 more elements
A method for repairing out a defective element in a memory device comprising the steps of:
- identifying a defective element;
- identifying a first column segment of a first redundant column of said memory device, said first column segment being programmably offset from at least one column segment of a second redundant column of said memory device;
- and
- activating said first column segment to repair out said defective element.
1 more element
A method for repairing out a defective memory cell in a memory device, said method comprising the steps of:
- locating said defective memory cell in said memory device;
- identifying a sense amplifier connected to said defective memory cell;
- programming a segment of a first redundant column such that said segment spans all memory cells connected to said sense amplifier, said programmed segment of said first redundant column being offset with respect to at least one segment of a second redundant column;
- and
- repairing out said defective memory cell with said segment of said first redundant column.
2 more elements
Dependencies are inferred from the claim text.