US 6,307,793 B1 · Memory device, coupling noise eliminator, and coupling noise elimination method

Abstract

In a memory device having a plurality of memory cells arranged in matrix as a memory cell array, pull down transistors (21, 22) are formed on a write word line wrword0 where the write word line wrword0 is adjacent in configuration to a read word line rdword0. When the read word line rdword0 is a H level during data read from the memory cells, both the pull down transistors (21, 22) enter ON and the write word line wrword0 is set to a L level. Thereby, only a coupling noise voltage of a small magnitude is generated on the write word line wrword0 even if the read word line rdword0 adjacent to the write word line wrword0 is the H level. Because the coupling noise voltage generated is smaller than a threshold voltage Vth of a transfer gate (1) for data write of the memory cell, the transfer gate (1) cannot enter ON and no write error occurs.

Claims8

Dependent claims

A memory device comprising:

a memory cell array made up of a plurality of memory cells arranged in a matrix;
a first signal line configured to transfer a first control signal to read data from a memory cell in the memory cell array;
a second signal line adjacent in configuration to the first signal line, configured to transfer a second control signal to write data to a memory cell in the memory cell array, the first control signal and the second control signal being not generated simultaneously;
and
a first switching element of not less than one which enters ON/OFF state according to a level of the first control signal and configured to supply a desired voltage to the second signal line when the first switching element enters ON.

2 more elements

Dependencies are inferred from the claim text.

Memory device, coupling noise eliminator, and coupling noise elimination method

Life of this patent

Memory device, coupling noise eliminator, and coupling noise elimination method

Life of this patent

Abstract

Claims8