Read compression in a memory
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Dean Nobunaga
Life of this patent
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Abstract
A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.
Claims24
A memory device comprising:
- an array of memory cells;
- a plurality of data output buffers to provide data from the array to external nodes;
- and
- first and second parallel data paths between the array and the plurality of data output buffers, wherein the first data path comprises compression logic to compress the data from the array to a portion of the plurality of data output buffers.
A memory device comprising:
- a memory array with y-banks of memory cells arranged in rows and columns;
- x-output buffers coupled to the y-banks to provide data on x-output nodes;
- a first set of data paths coupled between the y-banks and the x-output buffers to couple data from x-columns of one of the y-banks to the x-output buffers;
- a second set of data paths coupled between the y-banks and the x-output buffers, the second set of data paths comprise compression logic to simultaneously couple x-columns from the y-banks to a portion of the x-output buffers;
- and
- multiplex circuitry coupled to the output buffers and the first and second sets of data paths to selectively couple the first or second data path to the output buffers.
A method of operating a memory comprising:
- initiating a read operation;
- coupling first data from an array to outputs through a first data path during the read operation;
- initiating a test operation;
- and
- coupling second data from the array to the outputs through a second data path during the test operation, the first and second data paths are coupled in parallel and the second data path comprises compression circuitry.
A non-volatile memory device comprising:
- an array of non-volatile memory cells arranged in rows and columns;
- a plurality of output buffers;
- a first selectable data path to couple read data from the array to the plurality of output buffers;
- a second selectable data path coupled in parallel with the first selectable data path to couple read data from the array to the plurality of output buffers, the second data path comprises first compression circuitry;
- and
- a third selectable data path coupled between the array and the plurality of output buffers, the third data path comprises second compression circuitry.
A non-volatile memory device comprising:
- an array of non-volatile memory cells arranged in blocks of memory cell rows and columns;
- a plurality of output buffers;
- a first selectable data path coupled between a block of the array and the plurality of output buffers;
- a second selectable data path coupled in parallel with the first selectable data path to couple read data from the array to the plurality of output buffers, the second data path comprises first compression circuitry;
- and
- a third selectable data path to couple data between outputs of the first compression circuitry and the plurality of output buffers, the third data path comprises second compression circuitry.
Dependencies are inferred from the claim text.