Semiconductor memory cell having read/write circuit capable of performing random access

A read/write circuit for a cell array which is configured by arranging a plurality of memory cells in a matrix form, wherein the memory cell accumulates charges therein in response to a level of a bit line at a write mode, while at a read mode, a transition is caused to occur on level of the bit line in response to the accumulated charges, said read/write circuit comprising:

• connection means for connecting the bit line to a line of a prescribed potential at the read mode;
• read means for reading data from the memory cell based on a decision as to whether the bit line is changed in level from the prescribed potential or not at the read mode;
• and
• write means for changing the level of the bit line to match with a level corresponding to the data which are read from the memory cell by the read means or data which are newly written into the memory cell.

A read/write circuit for a memory cell in which at a write mode, charges are accumulated in response to a level of a write bit line, while at a read mode, a transition is caused to occur on level of a read bit line in response to the accumulated charges, said read/write circuit comprising:

• connection means for connecting the read bit line to a line of a prescribed potential at the read mode;
• read means for reading data from the memory cell based on a decision as to whether the read bit line is changed in level from the prescribed potential or not at the read mode;
• and
• write means for changing the level of the write bit line to match with a level corresponding to the data which are read from the memory cell by the read means or data which are newly written into the memory cell.

A read/write circuit for a memory cell in which at a write mode, charges are accumulated in response to a level of a write bit line, while at a read mode, a transition is caused to occur on level of a read bit line in response to the accumulated charges, said read/write circuit comprising:

• read means for reading data from the memory cell based on a decision as to whether the read bit line is changed in level from the prescribed potential or not at the read mode;
• write means for changing the level of the write bit line to match with a level corresponding to the data which are read from the memory cell by the read means or data which are newly written into the memory cell;
• and
• preparation means for at the read mode, setting the level of the write bit line at its previous level which is previously set to the write bit line before the write means changes the level of the write bit line, and/or for at the write mode, setting the level of the read bit line at its previous level which is previously set to the read bit line before the memory causes the transition to occur on the level of the read bit line.

A read/write circuit for a memory cell in which at a write mode, charges are accumulated in response to a level of a write bit line, while at a read mode, a transition is caused to occur on a level of a read bit line in response to the accumulated charges, said read/write circuit comprising:

• read means for reading data from the memory cell at the read mode;
• write means for changing the level of the write bit line to match with a level corresponding to the data which is read from the memory cell by the read means or data which are newly written into the memory cell;
• and
• write preparation means for setting the level of the write bit line at its previous level which is previously set to the write bit line before the write means changes the level of the write bit line.

A read/write circuit for a cell array which is configured by arranging a plurality of memory cells in a matrix form, wherein the memory cell accumulates charges therein in response to a level of a write bit line at a write mode, while at a read mode, a transition is caused to occur on a level of a read bit line in response to the accumulated charges, said read/write circuit comprising:

• connection means for connecting the read bit line to a line of a prescribed potential at the read mode;
• read means for reading data from the memory cell based on a decision as to whether the read bit line is changed in level from the prescribed potential or not at the read mode;
• and
• write means for changing the level of the write bit line to match with a level corresponding to the data which are read from the memory cell by the read means or data which are newly written into the memory cell.

A read/write circuit for a cell array which is configured by arranging a plurality of memory cells in a matrix form, wherein the memory cell accumulates charges therein in response to a level of a read bit line at a write mode, while at a read mode, a transition is caused to occur on a level of a write bit line in response to the accumulated charges, said read/write circuit comprising:

• read means for reading data from the memory cell based on a decision as to whether the read bit line is changed in level from the prescribed potential or not at the read mode;
• write means for changing the level of the write bit line to match with a level corresponding to the data which are read from the memory cell by the read means or data which are newly written into the memory cell;
• and
• preparation means for at the read mode, setting the level of the write bit line at its previous level which is previously set to the write bit line before the write means changes the level of the write bit line, and/or for at the write mode, setting the level of the read bit line at its previous level which is previously set to the read bit line before the memory causes the transition to occur on the level of the read bit line.

A read/write circuit for a cell array which is configured by arranging a plurality of memory cells in a matrix form, wherein the memory cell accumulates charges therein in response to a level of a read bit line at a write mode, while at a read mode, a transition is caused to occur on a level of a write bit line in response to the accumulated charges, said read/write circuit comprising:

• read means for reading data from the memory cell at the read mode;
• write means for changing the level of the write bit line to match with a level corresponding to the data which is read from the memory cell by the read means or data which are newly written into the memory cell;
• and
• write preparation means for setting the level of the write bit line at its previous level which is previously set to the write bit line before the write means changes the level of the write bit line.