US 6,307,787 B1 · Burst read incorporating output based redundancy · patentgrep

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Abstract

A device for performing redundant reading in a flash memory is provided. The device includes arrays of regular memory cells and arrays of redundant memory cells. Some of the regular memory cells may be defective and those will have defective addresses. A regular sense amplifier will read the regular memory cells at their accessed address while at a time no later a redundant sense amplifier will read the redundant memory cells. A first array of CAM's will store the defective addresses of the defective memory cells while a second array of CAM's will store the input/output designators of the defective memory cells. Address matching circuitry will compare the accessed addresses with the defective addresses to determine whether the accessed address is defective. Before the end of the reading intervals of the sense amplifiers, decoding circuitry will decode the input/output designators of both the defective and non-defective memory cells. A multi-bit multiplexer stage will output either the contents of the regular memory cell or, if the address is defective, the contents of the redundant memory cell. The contents will be applied to the multiplexer output corresponding to the input/output designator of the memory cell.

Claims11

Dependent claims

A read redundancy assembly in a flash memory device, the assembly comprising:

an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;
the regular memory cell comprising a defective memory cell and non-defective memory cell, each regular memory cell having an input/output designator and a storage address;
a regular first memory cell comprising one of the regular memory cells;
a first address comprising the storage address of the regular first memory cell;
a defective first memory cell comprising one of the defective memory cells;
a defective address comprising the storage address of the defective first memory cell;
decoding circuitry configured to generate a defect decoding signal in response to the input/output designator of the defective first memory cell if said circuitry determines that the first address is the defective address, the defect decoding signal corresponding to said input/output designator;
the decoding circuitry being further configured to generate a regular decoding signal if said circuitry determines that the first address is not a defective address, the regular decoding signal corresponding to the input/output designator of the regular first memory cell;
a multiplexer stage having multiplex outputs, the multiplexer stage configured to select and apply at a multiplex first output a regular output signal in response to the regular first memory cell and in response to the regular decoding signal corresponding to the input/output designator of the regular first memory cell, the multiplex first output being the multiplex output corresponding to the input/output designator of the regular first memory cell;
and
the multiplexer stage being further configured to select and apply at a multiplex second output a redundant output signal in response to the redundant memory cell and in response to the defect decoding signal corresponding to the input/output designator of the defective first memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective first memory cell.

8 more elements

A read redundancy assembly in a flash memory device, the assembly comprising:

an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;
the regular memory cell comprising a defective memory cell and non-defective memory cell;
a stored word comprising a plurality of regular memory cells, each regular memory cell in a stored word having an input/output designator;
a storage address of the stored word;
a defective word comprising a stored word having a defective memory cell;
a non-defective word comprising a stored word having no defective memory cell;
a defective address comprising the storage address of the defective word;
a first array of one or more CAM's, the first array configured to store the defective address;
a second array of one or more CAM's, the second array configured to store the input/output designator of the defective memory cell;
address matching circuitry configured to compare the storage address with the defective address, said circuitry being further configured to generate a defective address match signal if the comparison determines that the storage address is the defective address;
the address matching circuitry being further configured to generate a non-defective address match signal if the comparison determines that the storage address is not a defective address;
decoding circuitry configured to generate a defect decoding signal in response to the input/output designator of the defective memory cell of the defective word having the accessed address and in response to the defective address match signal, the defect decoding signal corresponding to said input/output designator;
the decoding circuitry being further configured to generate separate regular decoding signals in response to the non-defective address match signal, the separate regular decoding signals corresponding to the separate input/output designators of the separate non-defective memory cells of the non-defective word having the accessed address;
a multiplexer stage having multiplex outputs, the multiplexer stage configured to select and apply at a multiplex first output a regular output signal in response to the regular memory cell and in response to the regular decoding signal corresponding to the input/output designator of such separate non-defective memory cell of such non-defective word, the multiplex first output being the multiplex output corresponding to the input/output designator of such separate non-defective memory cell;
and
the multiplexer stage being further configured to select and apply at a multiplex second output a redundant output signal in response to the redundant memory cell and in response to the defect decoding signal corresponding to the input/output designator of the defective memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective memory cell.

13 more elements

A read redundancy assembly in a flash memory device, the assembly comprising:

an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;
the regular memory cell comprising a defective memory cell and non-defective memory cell, each regular memory cell having an input/output designator and a storage address;
a regular sense amplifier configured to read the regular memory cell;
an accessed memory cell comprising the regular memory cell read by the regular sense amplifier;
an accessed address comprising the storage address of the accessed memory cell;
a redundant sense amplifier;
a defective address comprising the storage address of the defective memory cell;
the regular sense amplifier being configured to read the accessed memory cell during a first interval of time and generate during the first interval a regular signal;
the redundant sense amplifier being configured to read the redundant memory cell during a second interval of time and generate during the second interval a redundant signal, the second interval not extending substantially beyond the first interval;
address matching circuitry configured to compare the accessed address with the defective address, said circuitry being further configured to generate during a third interval of time a defective address match signal if the comparison determines that the accessed address is the defective address;
the address matching circuitry being further configured to generate during the third interval a non-defective address match signal if the comparison determines that the accessed address is not a defective address, the third interval not extending substantially beyond the first interval;
decoding circuitry configured to generate during a fourth interval the defective memory cell having the accessed address and in response to the defective address match signal, the defect decoding signal corresponding to said input/output designator;
the decoding circuitry being further configured to generate non-defective address match signal, the separate regular decoding signals corresponding to the separate input/output designators of the separate nondefective memory cells having the accessed address, the fourth interval not extending substantially beyond the first interval;
a multiplexer stage having multiplex outputs, the multiplexer stage configured to select and apply at a multiplex first output a regular output signal in response to the regular signal and in response to the regular decoding signal corresponding to the input/output designator of such separate non-defective memory cell, the multiplex first output being the multiplex output corresponding to the input/output designator of such separate non-defective memory cell;
and
the multiplexer stage being further configured to select and apply at a multiplex second output a redundant output signal in response to the redundant signal and in response to the defect decoding signal corresponding to the input/output designator of the defective memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective memory cell.

13 more elements

A read redundancy assembly in a flash memory device, the assembly comprising:

an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;
the regular memory cell comprising a defective memory cell and non-defective memory cell;
a stored word comprising a plurality of regular memory cells, each regular memory cell in a stored word having an input/output designator;
a storage address of the stored word;
a regular sense amplifier configured to read the regular memory cell of the stored word;
an accessed word comprising the stored word having the regular memory cell read by the regular sense amplifier;
an accessed address comprising the storage address of the accessed word;
a redundant sense amplifier;
a defective word comprising a stored word having a defective memory cell;
a non-defective word comprising a stored word having no defective memory cell;
a defective address comprising the storage address of the defective word;
a first array of one or more CAM's, the first array configured to store the defective address;
a second array of one or more CAM's, the second array configured to store the input/output designator of the defective memory cell;
the regular sense amplifier being configured to read the regular memory cell of the accessed word during a first interval of time and generate during the first interval a regular signal;
the redundant sense amplifier being configured to read the redundant memory cell during a second interval of time and generate during the second interval a redundant signal, the second interval not extending substantially beyond the first interval;
decoding circuitry configured to generate during a third interval of time a defect decoding signal in response to the input/output designator of the defective memory cell of the defective word having the accessed address if said circuitry determines that the accessed address is the defective address, the defect decoding signal corresponding to said input/output designator, the third interval not extending substantially beyond the first interval;
the decoding circuitry being further configured to generate during the third interval separate regular decoding signals if said circuitry determines that the accessed address is not a defective address, the separate regular decoding signals corresponding to the separate input/output designators of the separate non-defective memory cells of the non-defective word having the accessed address;
a multiplexer stage having multiplex outputs, the multiplexer stage configured to select and apply at a multiplex first output a regular output signal in response to the regular signal and in response to the regular decoding signal corresponding to the input/output designator of such separate non-defective memory cell of such non-defective word, the multiplex first output being the multiplex output corresponding to the input/output designator of such separate non-defective memory cell;
and
the multiplexer stage being further configured to select and apply at a multiplex second output a redundant output signal in response to the redundant signal and in response to the defect decoding signal corresponding to the input/output designator of the defective memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective memory cell.

17 more elements

A read redundancy assembly in a flash memory device, the assembly comprising:

an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;
the regular memory cell comprising a defective memory cell and non-defective memory cell;
a stored word comprising a plurality of regular memory cells, each regular memory cell in a stored word having an input/output designator;
a storage address of the stored word;
a regular sense amplifier configured to read the regular memory cell of the stored word;
an accessed word comprising the stored word having the regular memory cell read by the regular sense amplifier;
an accessed address comprising the storage address of the accessed word;
a redundant sense amplifier;
a defective word comprising a stored word having a defective memory cell;
a non-defective word comprising a stored word having no defective memory cell;
a defective address comprising the storage address of the defective word;
a first array of one or more CAM's, the first array configured to store the defective address;
a second array of one or more CAM's, the second array configured to store the input/output designator of the defective memory cell;
the regular sense amplifier being configured to read the regular memory cell of the accessed word during a first interval of time and generate during the first interval a regular signal;
the redundant sense amplifier being configured to read the redundant memory cell during a second interval of time and generate during the second interval a redundant signal, the second interval not extending substantially beyond the first interval;
address matching circuitry configured to compare the accessed address with the defective address, said circuitry being further configured to generate during a third interval of time a defective address match signal if the comparison determines that the accessed address is the defective address;
the address matching circuitry being further configured to generate during the third interval a non-defective address match signal if the comparison determines that the accessed address is not a defective address, the third interval not extending substantially beyond the first interval;
decoding circuitry configured to generate during a fourth interval of time a defect decoding signal in response to the input/output designator of the defective memory cell of the defective word having the accessed address and in response to the defective address match signal, the defect decoding signal corresponding to said input/output designator, the fourth interval not extending substantially beyond the first interval;
the decoding circuitry being further configured to generate during the fourth interval separate regular decoding signals in response to the non-defective address match signal, the separate regular decoding signals corresponding to the separate input/output designators of the separate non-defective memory cells of the non-defective word having the accessed address;
a multiplexer stage having multiplex outputs, the multiplexer stage configured to select and apply at a multiplex first output a regular output signal in response to the regular signal and in response to the regular decoding signal corresponding to the input/output designator of such separate non-defective memory cell of such non-defective word, the multiplex first output being the multiplex output corresponding to the input/output designator of such separate non-defective memory cell;
and
the multiplexer stage being further configured to select and apply at a multiplex second output a redundant output signal in response to the redundant signal and in response to the defect decoding signal corresponding to the input/output designator of the defective memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective memory cell.

19 more elements

A method of redundancy reading in a flash memory device, the device comprising:

an array of memory cells, the memory cells comprising a regular memory cell and a redundant memory cell;
the regular memory cell comprising a defective memory cell and non-defective memory cell;
a stored word comprising a plurality of regular memory cells, each regular memory cell in a stored word having an input/output designator;
a storage address of the stored word;
a regular sense amplifier configured to read the regular memory cell of the stored word;
an accessed word comprising the stored word having the regular memory cell read by the regular sense amplifier;
an accessed address comprising the storage address of the accessed word;
a redundant sense amplifier;
a defective word comprising a stored word having a defective memory cell;
a non-defective word comprising a stored word having no defective memory cell;
a defective address comprising the storage address of the defective word;
a first array of one or more CAM's, the first array configured to store the defective address;
a second array of one or more CAM's, the second array configured to store the input/output designator of the defective memory cell;
the method comprising the acts of:
reading with the regular sense amplifier the regular memory cell of the accessed word during a first interval of time;
generating during the first interval a regular signal in response to such reading;
reading with the redundant sense amplifier the redundant memory cell during a second interval of time;
generating during the second interval a redundant signal in response to such reading, the second interval not extending substantially beyond the first interval;
comparing during a third interval of time the accessed address with the defective address, the third interval not extending substantially beyond the first interval;
generating during the third interval of time a defective address match signal if the comparison determines that the accessed address is the defective address;
generating during the third interval a non-defective address match signal if the comparison determines that the accessed address is not a defective address;
generating during a fourth interval of time a defect decoding signal in response to the input/output designator of the defective memory cell of the defective word having the accessed address and in response to the defective address match signal, the defect decoding signal corresponding to said input/output designator, the fourth interval not extending substantially beyond the first interval;
generating during the fourth interval separate regular decoding signals in response to the non-defective address match signal, the separate regular decoding signals corresponding to the separate input/output designators of the separate non-defective memory cells of the non-defective word having the accessed address;
selecting and applying at a multiplex first output a regular output signal in response to the regular signal and in response to the regular decoding signal corresponding to the input/output designator of such separate non-defective memory cell of such non-defective word, the multiplex first output being the multiplex output corresponding to the input/output designator of such separate non-defective memory cell;
and
selecting and applying at a multiplex second output a redundant output signal in response to the redundant signal and in response to the defect decoding signal corresponding to the input/output designator of the defective memory cell, the multiplex second output being the multiplex output corresponding to the input/output designator of the defective memory cell.

23 more elements

Dependencies are inferred from the claim text.