Negative gate erase

A method of erasing a dual bit memory cell adapted to operate in a single bit mode, the dual bit memory cell having a normal bit and a complimentary bit wherein only the normal bit is programmed during normal operation, comprising:

• applying a first erase pulse having a substantially large electrical field to each normal bit location, one normal bit location at a time until each normal bit location of a block hag received an erase pulse;
• performing a verification on a nonnal bit location in the block of memory to determine if the normal bit location is in a blank state;
• applying a second erase pulse to bits in normal column locations of the sector if it is determined that the normal bit location is not in a blank state;
• performing a verification on a complimentary bit location associated with the normal bit location to determine if the complimentary is in a blank state;
• and
• applying a third erase pulse to the bits in the complimentary column locations if it is determined that the complementary bit location is not in the blank state.

A system for erasing a dual bit memory cell adapted to operate in a single bit mode, the dual bit memory cell having a normal bit and a complimentary bit wherein only the normal bit is programmed during normal operation, comprising:

• an array of dual bit flash memory cells;
• an address decoder component coupled to the array of dual bit flash memory cells, the address decoder component being adapted to provide access to a normal bit and a complimentary bit of each of the dual bit flash memory cells;
• a voltage generator adapted to provide appropriate voltages for performing programming and erasure of normal bits and complimentary bits of the dual bit flash memory cells;
• and
• a command logic component including a state machine, the command logic and state machine being coupled to the array and the address component and being operable to control the voltage generator, the command logic component and state machine being adapted to receive an erase command and execute an erase algorithm that programs normal bits of the memory cells, applies a first erase pulse having a substantially large electrical field to each normal bit of an I/O, one I/O at a time, until each normal bit of a block of the array has received an erase pulse and then performs a first verification and erase on a normal bit location and a second verification and erase on a complimentary bit location associated with the normal bit location for every bit location in the block of the array.

A system for erasing dual bit flash memory cells operating in a single bit mode, comprising:

• means for applying a first erase pulse having a substantially large electrical field to each normal bit of an I/O, one I/O at a time, until each normal bit of a block of memory has received an erase pulse;
• means for performing verify erasure of normal bit locations in the block of memory to determine if the normal bit location is in a blank state;
• and
• means for performing verify erasure of complimentary bit locations in the block of memory to determine if the complimentary bit location is in a blank state.