Descending staircase read technique for a multilevel cell NAND flash memory device

A method for reading data from a multi-level memory, the method comprising:

• applying a descending staircase voltage to a selected word line of the memory, the descending staircase voltage including a sequence of read voltages chosen to distinguish possible stored levels in an accessed memory cell coupled to the selected word line;
• detecting a sense signal produced in response to the descending staircase voltage at the memory cell;
• and
• producing output data in response to the sense signal.

A multi-level memory comprising:

• an array of memory cells accessible through respective word lines and bit lines;
• a control circuit controlling embedded operations of the memory;
• a read voltage generating circuit to generate a descending staircase read voltage to a word line associated with a selected memory cell under control of the control circuit;
• and
• a read circuit including
• a latch circuit, and
• a switch circuit responsive to an evaluate/enable signal to selectively store a read state signal in the latch circuit in response to a sense signal generated from application of the descending staircase read voltage to the word line associated with the selected memory cell.

A memory device comprising:

• a plurality of memory cells, each memory cell capable of storing one of N possible levels;
• decoding means for selecting a word line associated with a selected address and a sense line associated with the selected address;
• control means operational during a read mode for applying consecutive values of a descending staircase read voltage to the selected word line and providing consecutive values of a multi-bit read state signal;
• and
• logic means coupled to the control means and the decoding means for storing in a memory means for storing data respective values of the read state signal for each respective value of the descending staircase read voltage.