Method and circuitry for bank tracking in write command sequence

A synchronous flash memory device comprising:

• an array of non-volatile memory cells arranged in a plurality of addressable blocks;
• and
• control circuitry to access the plurality of addressable blocks to perform an erase operation on memory cells contained in a first one of the plurality of addressable blocks, the control circuitry performs the erase operation in response to an externally provided command sequence comprising,
• an erase command accompanied by a bank address of the first one of the plurality of addressable blocks,
• an active command following the erase command, the active command indicates the bank address of the first one of the plurality of addressable blocks, and
• an erase confirm command following the active command and accompanied by the bank address of the first one of the plurality of addressable blocks.

A synchronous flash memory device comprising:

• an array of non-volatile memory cells arranged in a plurality of addressable blocks;
• and
• control circuitry to access the plurality of addressable blocks to perform a write operation on memory cells contained in a first one of the plurality of addressable blocks, the control circuitry performs the write operation in response to an externally provided command sequence comprising:
• a first write command accompanied by a bank address of the first one of the plurality of addressable blocks;
• an active command following the first write command, the active command indicates a row address and is accompanied by the bank address of the first one of the plurality of addressable blocks;
• and
• a second write command following the active command, the second write command indicates a row address and is accompanied by the bank address of the first one of the plurality of addressable blocks.

A memory system comprising:

• a memory controller;
• and
• a synchronous flash memory device coupled to the memory controller, the synchronous flash memory device comprising:
• an array of non-volatile memory cells arranged in a plurality of addressable blocks;
• and
• control circuitry to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks, the control circuitry performs the write or erase operation in response to a command sequence provided by the memory controller and prohibits the write or erase operation if a bank address provided by the memory controller changes during the externally provided command sequence.

A memory system comprising:

• a memory controller;
• and
• a synchronous flash memory device coupled to the memory controller, the synchronous flash memory device comprising:
• an array of non-volatile memory cells arranged in a plurality of addressable blocks;
• and
• control circuitry to access the plurality of addressable blocks to perform an erase operation on memory cells contained in a first one of the plurality of addressable blocks, the control circuitry performs the erase operation in response to a command sequence provided by the memory controller, the command sequence comprises:
• an erase command provided by the memory controller and accompanied by a bank address of the first one of the plurality of addressable blocks;
• an active command provided by the memory controller and following the erase command, the active command indicates the bank address of the first one of the plurality of addressable blocks;
• and
• an erase confirm command provided by the memory controller and following the active command and accompanied by the bank address of the first one of the plurality of addressable blocks.

A memory system comprising:

• a memory controller;
• and
• a synchronous flash memory device coupled to the memory controller, the synchronous flash memory device comprising:
• an array of non-volatile memory cells arranged in a plurality of addressable blocks;
• and
• control circuitry to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks, the control circuitry performs the write or erase operation in response to a command sequence provided by the memory controller, the command sequence comprises:
• a first write command provided by the memory controller and accompanied by a bank address of the first one of the plurality of addressable blocks;
• an active command provided by the memory controller and following the first write command, the active command indicates a row address and is accompanied by the bank address of the first one of the plurality of addressable blocks;
• and
• a second write command provided by the memory controller and following the active command, the second write command indicates a row address and is accompanied by the bank address of the first one of the plurality of addressable blocks.

A method of operating a synchronous flash memory device, the method comprising:

• receiving either an erase or a write command sequence having X commands with the synchronous flash memory device;
• receiving a memory array bank address with the synchronous flash memory device during the command sequence;
• monitoring the bank address with the synchronous flash memory device;
• and
• prohibiting either an erase or a write operation if the monitored bank address changes during the erase or write command sequence.

A method of operating a synchronous flash memory device, the method comprising:

• receiving an erase command accompanied by the bank address;
• receiving an active command following the erase command, the active command indicates the bank address;
• receiving an erase confirm command following the active command and accompanied by the bank address;
• and
• performing an erase operation in response to receiving the erase confirmation command.

A method of operating a synchronous flash memory device, the method comprising:

• receiving an erase command accompanied by the bank address;
• receiving an active command following the erase command, the active command indicates the bank address;
• and
• receiving an erase confirm command following the active command and accompanied by the bank address.