Non-volatile latch with program strength verification
AssigneeNational Semiconductor Corporation
InventorGregory J. Smith
Life of this patent
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Abstract
An improved approach to examining program strength of non-volatile latches is disclosed. The program strength is able to be evaluated by inferring floating gate charge of memory elements of the non-volatile latches as indicated by current characteristics of the memory elements. Access to the program charge or the internal currents is facilitated by monitoring circuitry provided integral with the non-volatile latches.
Claims17
A non-volatile memory circuit, comprising:
- a non-volatile memory cell capable of being programmed into a programmed state;
- and
- a monitoring circuit operatively connected to said non-volatile memory cell, said monitoring circuit being configured to measure strength of the programming of said non-volatile memory cell in the programmed state based on a measurement of a drain-to-source current for said non-volatile memory cell.
A non-volatile memory circuit, comprising:
- a non-volatile memory cell capable of being programmed into a programmed state;
- means for measuring drain-to-source current for said non-volatile memory cell to infer strength of the programming of said non-volatile memory cell in the programmed state;
- and
- a buffer configured to output an output signal in accordance with the programmed state of said non-volatile memory cell.
A method for examining program strength of a previously programmed non-volatile memory latch provided within an integrated circuit, said method comprising:
- setting external test control signals that provide electrical connection to the non-volatile memory latch;
- and
- determining a programming strength for the non-volatile memory latch via the electrical connection provided to the non-volatile memory latch, the programming strength being determined using measurement of a drain-to-source current for the non-volatile memory latch.
Dependencies are inferred from the claim text.