Integrated memory having 2-transistor/2-capacitor memory cells

Abstract

An integrated memory includes word lines and bit lines intersecting each other at crossover points. The bit lines are combined into bit line pairs and the bit line pairs are interleaved by having at least one of the bit lines of one bit line pair disposed between the two bit lines of another bit line pair. 2-transistor/2-capacitor memory cells each have two 1-transistor/1-capacitor memory cells each disposed at a respective one of the crossover points. Each of the two 1-transistor/1-capacitor memory cells of the 2-transistor/2capacitor memory cells have a selection transistor connected to one of the two bit lines of a respective one of the bit line pairs and to at least one of the word lines. The selection transistors may be simultaneously activated for simultaneously accessing the two 1-transistor/1-capacitor memory cells of one of the 2-transistor/2-capacitor memory cell.

Dependencies are inferred from the claim text.