Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
AssigneeMicron Technology, Inc.
InventorsJames P. Nuxoll, Steven L. Hamren
Life of this patent
Estimating the term…
Abstract
Disclosed are semiconductor devices having terminal arrangements in which mirrored pairs of the semiconductor devices can be tested by a common test device.
Claims26
A semiconductor chip device, comprising:
- at least one semiconductor component, and
- a plurality of terminals, each of said terminals being connected to internal circuitry of said component, said plurality of terminals comprising at least one input-output terminal, at least one input only terminal, at least one ground terminal, at least one power for CMOS input and output pins terminal, at least one power for the RDRAM core and interface logic or for the RDRAM analog circuitry terminal, and at least one power for threshold reference voltage for RSL signals terminal, said terminals being arranged in a terminal arrangement such that a mirror image of said semiconductor chip would have an input-output terminal at positions corresponding to positions on said semiconductor chip device where there is an input-output terminal, said mirror image of said semiconductor chip would have an input only terminal at positions corresponding to positions on said semiconductor chip device where there is an input only terminal, said mirror image of said semiconductor chip would have a ground terminal at positions corresponding to positions on said semiconductor chip device where there is a ground terminal, said mirror image of said semiconductor chip would have a power for CMOS input and output pins terminal at positions corresponding to positions on said semiconductor chip device where there is a power for CMOS input and output pins terminal, said mirror image of said semiconductor chip would have a power for the RDRAM core and interface logic or for the RDRAM analog circuitry terminal at positions corresponding to positions on said semiconductor chip device where there is a power for the RDRAM core and interface logic or for the RDRAM analog circuitry terminal, and said mirror image of said semiconductor chip would have a power for threshold reference voltage for RSL signals terminal at positions corresponding to positions on said semiconductor chip device where there is a power for threshold reference voltage for RSL signals terminal.
A memory chip device, comprising:
- at least one memory circuit, and a plurality of externally accessible terminals, said terminals being arranged in six columns and nine rows, said terminals being arranged in said columns and rows according to the following table;
- DQ8 GND SIO0 SIO1 GND DQ7 DQ3 VCMOS DQ6 DQ5 VDD DQ4 DQ0 VDD DQ2 DQ1 VDD DQ0 RQ4 GND RQI RQ2 GND RQ3 RQ0 VDD RQ7 RQ6 VDD RQ5 CTMN GND VREF VDDa GNDa CFMN CTM GND DQI DQ2 GND CFM DQ3 VCMOS DQ6 DQ5 VDD DQ4 DQ8 GND SCK CMD GND DQ7.
A memory chip device, comprising:
- at least one memory circuit, and a plurality of externally accessible terminals, said terminals being arranged in six columns and nine rows, said terminals being arranged in said columns and rows according to the following table;
- DQ7 GND SIO1 SIO0 GND DQ8 DQ4 VDD DQ5 DQ6 VCMOS DQ3 DQ0 VDD DQ1 DQ2 VDD DQ0 RQ3 GND RQ2 RQ1 GND RQ4 RQ5 VDD RQ6 RQ7 VDD RQ0 CFMN GNDa VDDa VREF GND CTMN CFM GND DQ2 DQI GND CTM DQ4 VDD DQ5 DQ6 VCMOS DQ3 DQ7 GND CMD SCK GND DQ8.
A test device comprising a test head, said test head having a plurality of test device pads, said plurality of test pads including at least one input-output test pad, at least one input only test pad, at least one ground test pad, at least one power for CMOS input and output pins test pad, at least one power for the RDRAM core and interface logic or for the RDRAM analog circuitry test pad, and at least one power for threshold reference voltage for RSL signals test pad, said test pads being arranged such that a mirror image of said test head would have an input-output test pad at positions corresponding to positions on said test head where there is an input-output test pad, said mirror image of said test pad would have an input only test pad at positions corresponding to positions on said test head where there is an input only test pad, said mirror image of said test pad would have a ground test pad at positions corresponding to positions on said test head where there is a ground test pad, said mirror image of said test pad would have a power for CMOS input and output pins test pad at positions corresponding to positions on said test head where there is a power for CMOS input and output pins test pad, said mirror image of said test pad would have a power for the RDRAM core and interface logic or for the RDRAM analog circuitry test pad at positions corresponding to positions on said test head where there is a power for the RDRAM core and interface logic or for the RDRAM analog circuitry test pad, and said mirror image of said test pad would have a power for threshold reference voltage for RSL signals test pad at positions corresponding to positions on said test head where there is a power for threshold reference voltage for RSL signals test pad.
A memory module comprising:
- a module board;
- a first set of module board electrical connectors positioned on a first side of said module board in a first module board electrical connector arrangement and a second set of module board electrical connectors positioned on a second side of said module board in a second module board electrical connector arrangement;
- a first semiconductor chip device positioned on said first side of said module board, said first semiconductor chip device having a plurality of first chip terminals arranged in a first terminal arrangement, each of said first chip terminals being electrically connected to a respective one of said first electrical connectors;
- a second semiconductor chip device positioned on said second side of said module board, said second semiconductor chip device having a plurality of second chip terminals arranged in a second terminal arrangement, each of said second chip terminals being electrically connected to a respective one of said second electrical connectors;
- said first terminal arrangement being a mirror image of said second terminal arrangement, said first semiconductor chip device having a first terminal function assignment arrangement, said second semiconductor chip device having a second terminal function assignment arrangement which is identical to said first terminal function assignment arrangement.
A memory module comprising:
- a module board;
- a plurality of first module board electrical connector sets, each first module board electrical connector set comprising a set of electrical connectors, and a plurality of second module board electrical connector sets, each second module board electrical connector set comprising a set of electrical connectors;
- a plurality of first semiconductor chip devices, each of said first semiconductor chip devices having a set of first chip terminals arranged in a first terminal arrangement, each of the terminals in each said set of first chip terminals being electrically connected to a respective one of said first electrical connectors;
- a plurality of second semiconductor chip devices, each of said second semiconductor chip devices having a set of second chip terminals arranged in a second terminal arrangement, each of the terminals in each said set of second chip terminals being electrically connected to a respective one of said second electrical connectors;
- said first terminal arrangement being a mirror image of said second terminal arrangement, said first semiconductor chip device having a first terminal function assignment arrangement, said second semiconductor chip device having a second terminal function assignment arrangement which is identical to said first terminal function assignment arrangement.
A processor system comprising:
- a processor;
- and
- a memory device coupled to said processor, said memory device comprising:
- a module board;
- a first set of module board electrical connectors positioned on a first side of said module board in a first module board electrical connector arrangement and a second set of module board electrical connectors positioned on a second side of said module board in a second module board electrical connector arrangement;
- at least one first semiconductor chip device positioned on said first side of said module board, said first semiconductor chip device having a plurality of first chip terminals arranged in a first terminal arrangement, each of said first chip terminals being electrically connected to a respective one of said first electrical connectors;
- at least one second semiconductor chip device positioned on said second side of said module board, said second semiconductor chip device having a plurality of second chip terminals arranged in a second terminal arrangement, each of said second chip terminals being electrically connected to a respective one of said second electrical connectors;
- said first terminal arrangement being a mirror image of said second terminal arrangement, said first semiconductor chip device having a first function assignment arrangement, said second semiconductor chip device having a second function assignment arrangement which is identical to said first function assignment arrangement.
Dependencies are inferred from the claim text.