Low power priority encoder

Abstract

A CAM system is provided that includes a plurality of CAM arrays that are assigned different priority levels. Each CAM array generates a plurality of match control signals, wherein each of the CAM arrays asserts a match control signal for each detected match. The CAM system also includes a plurality of latch circuits, each being coupled to receive the match control signals from a corresponding CAM array. A latch control circuit is also coupled to receive the match control signals from the CAM arrays. In response, the latch control circuit causes one and only one of the latch circuits to latch the match control signals received from the corresponding CAM array. The latch circuit that latches the match control signals is the latch circuit corresponding with the highest priority CAM array to assert a match control signal. In one embodiment, the latch circuit is controlled by a latch enable signal. Power savings are realized because only one latch enable signal is asserted for any compare operation. Further power savings are realized because only one of the latch circuits switches its stored match control signals during a compare operation.

Dependencies are inferred from the claim text.