Digital zero-phase restart circuit

A digital timing loop circuit for use in a magnetic read channel comprising:

• an analog to digital converter means for sampling an analog input signal responsive to a sampling clock signal;
• a memory means for storing alternate samples from the analog to digital converter means so as to form even and odd streams of ADC samples;
• means for forming an initial phase estimate value responsive to the even and odd ADC sample streams, including a first digital accumulator for accumulating the even stream of ADC values and a second digital accumulator for accumulating the odd stream of ADC values;
• and
• digital phase interpolating means for shifting the sampling clock signal responsive to the initial phase estimate value at the beginning of the read operation so as to bring the sampling clock signal into alignment with the said analog input signal without halting the sampling clock.

A digital timing loop circuit for synchronizing a magnetic recording read channel comprising:

• an ADC for sampling an analog input signal responsive to a sampling clock signal;
• a phase detector for comparing a phase of the analog input signal as reflected in the ADC sample stream to the phase of the sampling clock signal to form a phase error signal;
• an integrator circuit for continually summing the phase error signal to form a phase select signal;
• a phase interpolator for digitally adjusting the phase of a reference clock signal that provides the sampling clock signal, responsive to the phase select signal, for aligning the sampling clock signal to the analog input signal during steady state operation;
• and
• a digital zero-phase restart circuit coupled to the integrator to adjust the phase select signal based upon an initial phase estimate at the beginning of a read operation, wherein the digital zero-phase restart circuit includes means for determining the initial phase estimate by an arctan lookup method based on even and odd ADC sample streams.

A zero-phase restart (ZPR) circuit for use in a magnetic read channel receiving first and second series of digital sample values to provide an initial phase estimate value, the ZPR circuit comprising:

• a first accumulator for accumulating the first digital sample values over a selected integration period to form an accumulated cosine value;
• a second accumulator for accumulating the second digital sample values over the same selected integration period to form an accumulated sine value;
• and
• an arctan lookup table coupled to the first and second accumulators to provide the initial phase estimate value as an arctan function of the accumulated sine and cosine values.

A zero-phase restart (ZPR) circuit for use in a magnetic read channel receiving first and second series of digital sample values ADC0, ADC1 to provide an initial phase estimate value, the ZPR circuit comprising:

• a first accumulator for accumulating the first digital sample values over a selected integration period to form an accumulated cosine value;
• a second accumulator for accumulating the second digital sample values over the same selected integration period to form an accumulated sine value;
• and
• a Peak_at_one logic circuit for comparing the accumulated sine value to the accumulated cosine value and providing a Peak_at_one logic signal indicating whether or not the first series of digital sample values (ADC0) correspond to zero crossing samples (sine), and the second series of digital sample values (ADC1) correspond to peak samples (cosine).

A digital timing loop circuit for use in a magnetic read channel comprising:

• an analog to digital converter means for sampling an analog input signal responsive to a sampling clock signal;
• a memory means for storing alternate samples from the analog to digital converter means so as to form even and odd streams of ADC samples representing orthogonal sine and cosine components of said analog input signal;
• means for forming an initial phase estimate value responsive to the even and odd ADC sample streams;
• and
• digital phase interpolating means for shifting the sampling clock signal responsive to the initial phase estimate value at the beginning of the read operation so as to bring the sampling clock signal into alignment with the said analog input signal without halting the sampling clock.

A digital timing loop circuit for use in a magnetic read channel comprising:

• an analog to digital converter means for sampling an analog input signal responsive to a sampling clock signal;
• a memory means for storing alternate samples from the analog to digital converter means so as to form even and odd streams of ADC samples;
• means for forming an initial phase estimate value responsive to the even and odd ADC sample streams;
• digital phase interpolating means for shifting the sampling clock signal responsive to the initial phase estimate value at the beginning of the read operation so as to bring the sampling clock signal into alignment with the said analog input signal without halting the sampling clock;
• and
• a multiplier for selectively multiplying alternate samples from the ADC by +1 or −1 to store in said memory means, so as to form said even and odd streams of the ADC samples representing orthogonal sine and cosine components of said analog input signal.