Input circuit for an image processor

A circuit for use with an imager capable of capturing an image, comprising:

• a memory configured to:
• during a first time interval, store a first representation of a first subimage of the image from the imager, and
• during a second time interval, receive an update from the imager and use the update and the first representation to store a second representation of a second subimage of the image, the first subimage partially overlapping the second subimage and the update representing a portion of the second subimage not present in the first subimage, wherein the memory includes memory cells configured to shift the first representation among the memory cells to form the second representation;
• and
• an output circuit configured to:
• during the first time interval, use the first representation to generate output signals representative of the first subimage, and
• during the second time interval, use the second representation to generate output signals representative of the second subimage,
• wherein the second subimage is offset from the first subimage along one of at least three different directions,
• wherein during the second time interval, the memory cells are further configured to shift the first representation among the cells along said one of the directions, and
• wherein the memory further comprises at least three shift register banks, each different shift register bank associated with a different one of the directions and operable to receive the update when the direction associated with the bank corresponds to said one of the directions.

A method of processing an image, comprising:

• storing a first representation of a first subimage of the image, said first subimage being less than the whole image and said first representation being offset from the first subimage along one of at least two different directions;
• during a first time interval, generating output signals representative of the first subimage;
• during a second time interval, receiving an update representing an additional portion of the image;
• using the update and the first representation to store a second representation of a second subimage of the image by including an operation to shift the first representation among memory cells along one of the at least two different directions, the first subimage partially overlapping the second subimage and the update representing a portion of the second subimage not present in the first subimage;
• using the second representation to generate output signals representative of the second subimage;
• and
• receiving the update in one of at least two different shift register banks based on the direction, each different shift register bank associated with a different one of the directions.

A circuit for loading a second subimage of an image captured by an imager, the second subimage partially overlapping a first subimage of the image and being partially offset from the first subimage along one of at least two directions, the imager capable of furnishing a first representation of the first subimage and an update representing a portion of the second subimage not present in the first subimage, comprising:

• a memory comprises at least two shift registers banks, each different shift register bank associated with a different one of the directions and configured to receive the update when the second subimage is offset from the first subimage along the direction;
• the memory cells connected to the banks and configured to:
• during a first time interval, store the first representation in first, second and third groups of the memory cells, and
• during the second time interval,
• discard a portion of the first representation stored in the second group of the memory cells,
• use the third group of the memory cells to shift the first representation from the first group of the memory cells toward the second group of the memory cells, and
• store the update in the first group of the memory cells;
• and
• digital-to-analog converters, each different digital-to-analog converter connected to a different one of the memory cells, the digital-to-analog converters configured to:
• during the first time interval, generate output signals representative of the first representation, and
• during the second time interval, generate output signals representative of the second representation.