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US 6,307,436 B1Granted
Predistortion type linearizer with a resonant circuit and common gate FET
AssigneeNEC Corporation
InventorGary Hau
Life of this patent
Estimating the term…
Abstract
This invention relates to an electronic circuit (predistortion type linearizer) for linearizing the nonlinear responses of amplifiers, to achieve low distortion, wide-dynamic range amplification particularly suitable for cellular handsets application.
Claims10
A predistortion type linearizer comprising:
- an input and an output;
- a ground node;
- an FET having a drain node, a gate node and a source node;
- a resonant circuit having an input node and an output node;
- a first, second and third inductor each having an input node and an output node;
- a first, second and third capacitor each having an input node and an output node;
- a resistor having an input node and an output node;
- said input node and said output node of said resonant circuit connected to said drain node and said source node of said FET respectively;
- said input node of said first inductor connected to said gate node of said FET;
- said input node of said first capacitor connected to said output node of said first inductor;
- said output node of said first capacitor connected to said ground node;
- a gate control voltage node connected to said input node of said resistor;
- said output node of said resistor connected to said output node of said first inductor;
- said input node and said output node of said second inductor connected to said drain node of said FET and said ground node respectively;
- said input node and said output node of said third inductor connected to said source node of said FET and said ground node respectively;
- said input node and said output node of said second capacitor connected to said input and said drain node of said FET respectively;
- and
- said input node and said output node of said third capacitor connected to said source node of said FET and said output respectively.
15 more elements
A predistortion type linearizer comprising:
- an input and an output;
- a ground node;
- an FET having a drain node, a gate node and a source node;
- a resonant circuit having an input node and an output node;
- a first, second and third inductor each having an input node and an output node;
- a first, second, third and fourth capacitor each having an input node and an output node;
- a resistor having an input node and an output node;
- said input node and said output node of said resonant circuit connected to said drain node and said source node of said FET respectively;
- said input node of said first inductor connected to said gate node of said FET;
- said input node of said first capacitor connected to said output node of said first inductor;
- said output node of said first capacitor connected to said ground node;
- a gate control voltage node connected to said input node of said resistor;
- said output node of said resistor connected to said output node of said first inductor;
- said input node and said output node of said second inductor connected to said drain node of said FET and said input node of said second capacitor respectively;
- said output node of said second capacitor connected to said ground node;
- a DC voltage source connected between said output node of said second inductor and said ground node;
- said input node and said output node of said third inductor connected to said source node of said FET and said ground node respectively;
- said input node and said output node of said third capacitor connected to said input and said drain node of said FET respectively;
- and
- said input node and said output node of said fourth capacitor connected to said source node of said FET and said output respectively.
17 more elements
Dependencies are inferred from the claim text.