Programmable impedance control output circuit and programmable impedance control method thereof in semiconductor device

An impedance control output circuit of a semiconductor device, comprising:

• an impedance detector having a transistor way adapted to respond to the first control code data and an offset transistor array adapted to respond to the second control code data, the impedance detector outputting a first reference voltage from a first common node of the transistor and offset transistor arrays and a pad voltage from a second common node of the transistor and offset transistor array;
• a comparison part having:
• a first comparator adapted to output a first up/down control signal by comparing the first reference voltage to the pad voltage;
• and
• a second comparator adapted to output a second up/down control signal by comparing the first reference voltage to a second reference voltage, the second reference voltage output by a resistant voltage divider;
• a counting part having:
• a first counter that performs an up/down counting in response to the first up/down control signal to thereby generate a first control code data for operating transistors of the transistor array;
• and
• a second counter that performs an up/down counting in response to the second up/down control signal to thereby generate a second control code data for operating transistors of the offset transistor array;
• a higher code selector having a first higher code selector to select a first control code data having a higher code value by latching the first control code data and comparing it with a first control code data applied from the following latch cycle and a second higher code selector to select a second control code data having a higher code value by latching the second control code data and comparing it with a second control code data applied from the following latch cycle;
• an impedance driving part having a first impedance driver to generate buffer driving codes in response to the fit control code data selected by the higher code selector and a second impedance driver to generate offset buffer driving codes in response to the second control code data selected by the higher code selector;
• a data output buffer having a plurality of unit output buffers to be selectively enabled in response to respective bit states of the buffer driving codes and offset buffer driving codes for allowing only the unit output buffers to be enabled to receive and buffer pairs of memory cell data and outputting them as pull-up and pull-down output data and offset pull-up and pull-down output data;
• an off-chip driver having transistor array and offset transistor array arranged in symmetry with a plurality of transistors for generating output data to an array common node by turning on transistors of an array respectively responding to a state of each type of output data and providing the impedance-matched output data through the output pad connected with the array common node;
• and
• a constant code detecting part having first and second constant code detectors for detecting constant codes in response to the first and second control code data selected by the higher code selector for generating mode control signals to alternately perform the first mode by which the first reference voltage and pad voltage are compared each other and the second mode by which the second reference voltage and the first reference voltage are compared each other.

A programmable impedance control output circuit of a semiconductor device, comprising:

• an impedance detector having a transistor array responsive to a first control code data and an offset transistor array responsive to a second control code data for respectively outputting a first reference voltage from a first common node in the transistor and offset transistor arrays and a pad voltage from a second common node;
• a comparison part having:
• a first comparator for outputting a first up/down control signal by comparing the first reference voltage and the pad voltage;
• and
• a second comparator for outputting a second up/down control signal by comparing the first reference voltage and a second reference voltage, the second reference voltage being output by a resistant voltage divider;
• a counting part having:
• a first counter that performs an up/down counting in response to the first up/down control signal to thereby generate a first code data for operating transistors of the transistor array;
• and
• a second counter that performs an up/down counting in response to the second up/down control signal to thereby generate a second control code data for operating transistors of the offset transistor array;
• a higher code selector having:
• a first higher code selector to select a first control code data having a higher code value by latching the first control code data and comparing it with a first control code data applied from a following latch cycle;
• and
• a second higher code selector to select a second control code data having a higher code value by latching the second control code data and comparing it with a second control code data applied from a following latch cycle;
• an impedance driving part having:
• a first impedance driver to generate buffer driving codes in response to the first control code data selected by the higher code selector;
• and
• a second impedance driver to generate offset buffer driving codes in response to the second control code data selected by the higher code selector;
• a data output buffer having a plurality of unit output buffers to be selectively enabled in response to respective bit states of the buffer driving codes and offset buffer driving codes for enabling only unit output buffers to receive, buffering pairs of memory cell data and outputting them as pull-up and pull-down output data and offset pull-up and pull-down output data accordingly;
• an off-chip driver having transistor array and offset transistor array arranged in symmetry with a plurality of transistors for generating output data to an array common node by turning on transistors of an array respectively responding to a state of each type of output data and providing impedance-matched output data through an output pad connected with the array common node;
• and
• a constant code detecting part having first and second constant code detectors to detect constant codes in response to the first and second control code data selected by the higher code selector for generating mode control signals to alternately perform a first mode by which the first reference voltage and pad voltage are compared each other and a second mode by which the second reference voltage and the first reference voltage are compared each other.

The claim, as defined in clam 23, wherein the transistor array of the off-chip driver includes:

• pairs of NMOS transistors arranged in symmetry from an output common node commonly connecting source and drain terminals which are respectively connected to a supply voltage and a ground voltage, the NMOS transistors having different driving capacities to set a level of output data at the output common node by being turned on/off in response to the pull-up and pull-down output data respectively applied to gate terminals;
• and
• wherein the offset transistor array of the offset driver includes:
• pairs of offset NMOS transistors arranged in symmetry from an output common node commonly connecting source and drain terminals which are respectively connected to a supply voltage and a ground voltage, the offset NMOS transistors having different driving capacities to set a level of output data at the output common node by being turned on/off in response to the offset pull-up and offset pull-down output data respectively applied to gate terminals.

A programmable impedance control output circuit of a semiconductor device comprising:

• a clock generating unit for generating a clock control signal relating to impedance matching and shifting it to a internal circuit part;
• an impedance detector having a transistor array responsive to a first control code data and an offset transistor array responsive to a second control code data for respectively outputting first reference voltage from the first common node of the arrays and pad voltage from the second common node;
• a comparison part having a first comparator for outputting a first up/down control signal by comparison a first reference voltage and a pad voltage and a second comparator for outputting a second up/down control signal by comparing the first reference voltage and a second reference voltage, the second reference voltage being output by a resistant voltage divider;
• a counting part having a first counter that performs an up/down counting in response to the first up/down control signal to thereby generate a first control code data for operating transistors of the transistor array and a second counter that performs an up/down counting in response to the second up/down control signal to thereby generate a second control code data for operating transistors of the offset transistor array;
• a higher code selector having a first higher code selector to select a first control code data having a higher code value by latching the first control code data and comparing it with a first control code data applied from a following latch cycle, in order to set a higher control code data as a final value when a level of the pad voltage crosses that of the fast reference voltage in a first operation mode, and a second higher code selector to select a second control code data having a higher code value by latching the second control code data and comparing it with a second control code data applied from a following latch cycle, in order to set a higher control code data as a final value when a level of either the first reference voltage or the pad voltage crosses that of the second reference voltage in the first operation mode;
• an impedance driving part having a first impedance driver to generate buffer driving codes in response to the first control code data selected by the higher code selector and a second impedance driver to generate offset buffer driving codes in response to the second control code data selected by the higher code selector;
• a data output buffer having a plurality of unit output buffers to be selectively enabled in response to respective bit states of tee buffer driving codes and offset buffer driving codes for allowing only unit output buffers to be enabled to receive and buffer pairs of memory cell data and outputting them as pull-up and pull-down output data and offset pull-up and pull-down output data;
• an off-chip driver having transistor array and offset transistor array arranged in symmetry with a plurality of transistors for generating impedance-matched output data to an array common node by turning on the transistors of a corresponding array respectively responding to a state of each type of output data and providing impedance-matched output data through an output pad connected with the array common node;
• and
• a constant code detecting part having first and second constant code detectors that operate to be alternately enabled in response to the first and second control code data selected by the higher code selector for generating mode control signals to perform a first operation mode by which the first reference voltage and the pad voltage are compared each other and a reset operation mode by which the first reference voltage and the pad voltage are selectively compared with a second reference voltage.

A method for matching an output impedance of a semiconductor memory device, comprising:

• matching the output impedance by comparing a pad voltage of a pad connected to an external resistor having a preset resistance value to an array reference voltage to result in the pad voltage tracking the array reference voltage and accordingly performing an impedance driving process of a data output terminal (step 1);
• matching the output impedance to a reset a level of the array reference voltage by comparing a constant reference voltage set by a resistant voltage divider with the array reference voltage to result in the array reference voltage tracking the constant reference voltage and accordingly performing an impedance driving process of the data output terminal (step 2);
• matching the output impedance to a reset a level of the pad voltage by comparing the constant reference voltage wit the pad voltage to result in the pad voltage tracking the constant reference voltage and accordingly performing an impedance driving process of the data output terminal (step 3);
• and sequentially and repeatedly performing the first, second and third steps described above.