Slew rate/propagation delay selection circuit
AssigneeLSI Logic Corporation
InventorJason K. Hoff
Life of this patent
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and a control signal. The second circuit may be configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and the control signal.
Claims19
An apparatus comprising:
- a first circuit configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and control signal;
- and
- a second circuit configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and a digital complement of said control signal.
An apparatus comprising:
- means for generating a first output signal having a predetermined slew rate and a predetermined propagation delay in response to (i) a first input signal and (ii) a control signal;
- and
- means for generating a second output signal having a predetermined slew rate and a predetermined propagation delay in response to (i) a second input signal and (ii) a digital complement of said control signal.
A method of controlling the slew rate and propagation delay of an I/O signal comprising the steps of:
- (A) generating a first output signal having a predetermined slew rate and a predetermined propagation delay in response to (i) a first input signal and (ii) a control signal;
- and
- (B) generating a second output signal having a predetermined slew rate and a predetermined propagation delay in response to (i) a second input signal and (ii) a digital complement of said control signal.
An apparatus comprising:
- a first circuit configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and control signal;
- and
- a second circuit configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and said control signal, wherein:
- said first circuit comprises:
- an input circuit configured to generate a first and a second intermediate signal in response to said first input signal;
- an output circuit configured to generate said first output signal in response to (i) said first intermediate signal, (ii) said control signal, and (iii) a first load signal;
- and
- is a feedback circuit configured to generate said first load signal in response to said second intermediate signal and said first output signal;
- and
- said second circuit comprises:
- a circuit configured to generate said second output signal in response to (i) said second input signal, (ii) said control signal, and (iii) a second load signal;
- and
- a feedback circuit configured to generate said second load signal in response to (i) said second input signal and (ii) said second output signal.
An apparatus comprising:
- a first circuit configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and a control signal;
- and
- a second circuit configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and said control signal, wherein said first circuit comprises:
- a first transistor connected to a first terminal of a resistor having a known resistance value;
- a second transistor connected to a second terminal of said resistor;
- a third transistor connected to a fourth transistor;
- and
- said fourth transistor connected to said first terminal of said resistor, wherein (i) an intermediate signal is presented to a gate of said first, said second and said third transistors, (ii) said control signal is presented to a gate of said fourth transistor, and (iii) said first output signal is presented at said first terminal of said resistor.
An apparatus comprising:
- a first circuit configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and control signal;
- and
- a second circuit configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and said control signal, wherein said second circuit comprises:
- a first transistor connected to a second transistor and a first terminal of a resistor having a known resistance value;
- and
- a third transistor connected to said second transistor and a second terminal of said resistor, wherein (i) said second input signal is presented to a gate of said first and said third transistors, (ii) said control signal is presented to a gate of said second transistor, and (iii) said second output signal is presented at said second terminal of said resistor.
Dependencies are inferred from the claim text.