Reference-free clock generator and data recovery PLL
AssigneeCypress Semiconductor Corporation
InventorsKamal Dalmia, Anil Agarwal
Life of this patent
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Abstract
An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.
Claims19
An apparatus comprising:
- a first circuit configured to generate (a) a first output signal having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate and (b) a first data signal having said second data rate;
- a second circuit configured to generate a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal;
- and
- a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal.
An apparatus comprising:
- means for generating (a) a first output signal having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate and (b) a first data signal having said second data rate;
- means for generating a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal;
- and
- means for generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
A method for clock data recovery comprising the steps of:
- (A) generating a first output signal having a first data rate in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate and (ii) a first data signal having said second data rate;
- (B) generating a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal;
- and
- (C) generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
An apparatus comprising:
- a first circuit configured to generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having said second data rate;
- a second circuit configured to generate a second output signal having a third data rate in response to (i) a divided version of said input signal and (ii) said clock signal;
- and
- a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal, wherein said first and said second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.
Dependencies are inferred from the claim text.