Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit

A clock monitor circuit, comprising:

• a first delay and clock signal generating circuit for receiving a clock signal, the first delay and clock signal generating circuit generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition;
• a second delay and clock signal generating circuit for receiving an inverted clock signal, the inverted clock signal being a substantial inverse of the clock signal and having a skew relative to the clock signal, the second delay and clock signal generating circuit generating a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the inverted clock signal makes a corresponding second transition;
• and
• a stop signal generating circuit adapted to generate a stop signal by logically manipulating the first and second internal clock signals, the stop signal having a first and a second state responsive to the logical manipulation of the first and second internal clock signals, the stop signal being in the first state in a standby mode;
• wherein the first delay and clock generating circuit comprises:
• a first delay circuit for generating a first delay pulse, the first delay pulse making a first change in logic states a first delay time after the clock signal makes a corresponding first change in logic states and making a second change in logic states a second delay time after the clock signal makes a corresponding second change in logic states;
• and
• a second logic gate for generating the first internal clock signal by logically manipulating the first delay pulse and the clock signal;
• wherein the first delay circuit includes a first plurality of serially connected inverters comprising:
• a first predetermined number of first inverters each having a first pull-up transistor and a first pull-down transistor, each first pull-up transistor having a small size and each first pull-down transistor having a large size;
• and
• a second predetermined number of second inverters each having a second pull-up transistor and a second pull-down transistor, the second pull-up transistor having a large size and the second pull-down transistor having a small size;
• and
• wherein the first and second inverters are alternately serially connected such that an output signal from a first inverter is an input signal to a second inverter and the first inverter in a first position is responsive to the clock signal.

A clock monitor circuit, comprising:

• a first delay and clock signal generating circuit for receiving a clock signal, the first delay and clock signal generating circuit generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition;
• a second delay and clock signal generating circuit for receiving an inverted clock signal, the inverted clock signal being a substantial inverse of the clock signal and having a skew relative to the clock signal, the second delay and clock signal generating circuit generating a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the inverted clock signal makes a corresponding second transition;
• a stop signal generating circuit adapted to generate a stop signal by logically manipulating the first and second internal clock signals, the stop signal having a first and a second state responsive to the logical manipulation of the first and second internal clock signals, the stop signal being in the first state in a standby mode;
• wherein the first delay and clock generating circuit comprises:
• a first delay circuit for generating a first delay pulse, the first delay pulse making a first change in logic states a first delay time after the clock signal makes a corresponding first change in logic states and making a second change in logic states a second delay time after the clock signal makes a corresponding second change in logic states;
• and
• a second logic gate for generating the first internal clock signal by logically manipulating the first delay pulse and the clock signal;
• wherein the second delay and clock generating circuit comprises:
• a second delay circuit for generating a second delay pulse, the second delay pulse making the first change in logic states the first delay time after the inverted clock signal makes a corresponding first change in logic states and making the second change in logic states the second delay time after the inverted clock signal makes a corresponding second change in logic states;
• a third logic gate for generating the second internal clock signal by logically manipulating the second delay pulse and the inverted clock signal;
• wherein the second delay circuit includes a second plurality of serially connected inverters comprising:
• a third predetermined number of third inverters each having a third pull-up transistor and a third pull-down transistor, the third pull-up transistor having a small size and the third pull-down transistor having a large size;
• and
• a fourth predetermined number of fourth inverters each having a fourth pull-up transistor and a fourth pull-down transistor, the fourth pull-up transistor having a large size and the fourth pull-down transistor having a small size;
• and
• wherein the third and fourth inverters are alternately serially connected such that an output signal from a third inverter is an input signal to a fourth inverter and the third inverter in a first position is responsive to the inverted clock signal.

A semiconductor memory device operating synchronous with a clock signal, comprising:

• first delay and clock signal generating means for receiving a clock signal and generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition;
• second delay and clock signal generating means for receiving an inverted clock signal and generating a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the inverted clock signal makes a corresponding second transition;
• and
• first logic means for generating a stop signal by logically manipulating the first and second internal clock signals, the stop signal having a first logic state when the clock and inverted clock signals are in a first state
• wherein the first delay and clock signal generating means includes a first plurality of serially connected inverters comprising:
• a first predetermined number of first inverters each having a first pull-up transistor and a first pull-down transistor, each first pull-up transistor having a small size and each first pull-down transistor having a large size;
• and
• a second predetermined number of second inverters each having a second pull-up transistor and a second pull-down transistor, the second pull-up transistor having a large size and the second pull-down transistor having a small size;
• and
• wherein the first and second inverters are alternately serially connected such that an output signal from a first inverter is an input signal to a second inverter and the first inverter in a first position is responsive to the clock signal.

A clock monitor circuit, comprising:

• first delay and clock signal generating means for receiving a clock signal and generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition;
• second delay and clock signal generating means for receiving an inverted clock signal and generating a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the inverted clock signal makes a corresponding second transition;
• and
• first logic means for generating a stop signal by logically manipulating the first and second internal clock signals, the stop signal having a first logic state when the clock and inverted clock signals are in a first state and the device is in a standby mode;
• wherein the first delay and clock generating means comprises:
• first delay means for generating a first delay pulse, the first delay pulse making a first change in logic states a first delay time after the clock signal makes a corresponding first change in logic states and making a second change in logic states a second delay time after the clock signal makes a corresponding second change in logic states;
• and
• second logic means for generating the first internal clock signal by logically manipulating the first delay pulse and the clock signal;
• wherein the first delay means includes a first plurality of serially connected inverters comprising:
• a first predetermined number of first inverters each having a first pull-up transistor and a first pull-down transistor, each first pull-up transistor having a small size and each first pull-down transistor having a large size;
• and
• a second predetermined number of second inverters each having a second pull-up transistor and a second pull-down transistor, the second pull-up transistor having a large size and the second pull-down transistor having a small size;
• and
• wherein the first and second inverters arc alternately serially connected such that an output signal from a first inverter is an input signal to a second inverter and the first inverter in a first position is responsive to the clock signal.

A clock monitor circuit, comprising:

• first delay and clock signal generating means for receiving a clock signal and generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition;
• second delay and clock signal generating means for receiving an inverted clock signal and generating a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the inverted clock signal makes a corresponding second transition;
• and
• first logic means for generating a stop signal by logically manipulating the first and second internal clock signals, the stop signal having a first logic state when the clock and inverted clock signals are in a first state and the device is in a standby mode;
• wherein the first delay and clock generating means comprises:
• first delay means for generating a first delay pulse, the first delay pulse making a first change in logic states a first delay time after the clock signal makes a corresponding first change in logic states and making a second change in logic states a second delay time after the clock signal makes a corresponding second change in logic states;
• and
• second logic means for generating the first internal clock signal by logically manipulating the first delay pulse and the clock signal;
• wherein the second delay and clock generating means comprises:
• second delay means for generating a second delay pulse, the second delay pulse making the first change in logic states the first delay time after the inverted clock signal makes a corresponding first change in logic states and making the second change in logic states the second delay time after the inverted clock signal makes a corresponding second change in logic states;
• and
• third logic means for generating the second internal clock signal by logically manipulating the second delay pulse and the inverted clock signal;
• wherein the second delay means includes a second plurality of serially connected inverters comprising:
• a third predetermined number of third inverters each having a third pull-up transistor and a third pull-down transistor, the third pull-up transistor having a small size and the third pull-down transistor having a large size;
• and
• a fourth predetermined number of fourth inverters each having a fourth pull-up transistor and a fourth pull-down transistor, the fourth pull-up transistor having a large size and the fourth pull-down transistor having a small size;
• and
• wherein the third and fourth inverters are alternately serially connected such that an output signal from a third inverter is an input signal to a fourth inverter and the third inverter in a first position is responsive to the inverted clock signal.

A method for detecting a clock signal in a synchronous semiconductor memory device to thereby reduce power consumption, comprising:

• receiving the clock signal and an inverted clock signal, the inverted clock signal having a skew relative to the clock signal;
• generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition;
• generating a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the inverted clock signal makes a corresponding second transition;
• and
• generating a stop signal by logically manipulating the first and second internal clock signals, the stop signal having a first logic state when the clock and inverted clock signal are in the first logic state
• wherein generating the first internal clock signal comprises:
• serially connecting a first plurality of inverters comprising:
• a first predetermined number of first inverters each having a first pull-up transistor and a first pull-down transistor, each first pull-up transistor having a small size and each first pull-down transistor having a large size;
• and
• a second predetermined number of second inverters each having a second pull-up transistor and a second pull-down transistor, the second pull-up transistor having a large size and the second pull-down transistor having a small size;
• and
• wherein the first and second inverters are alternately serially connected such that an output signal from a first inverter is an input signal to a second inverter and the first inverter in a first position is responsive to the clock signal
• wherein generating the second internal clock signal comprises:
• serially connecting a second plurality of inverters comprising:
• a third predetermined number of third inverters each having a third pull-up transistor and a third pull-down transistor, the third pull-up transistor having a small size and the third pull-down transistor having a large size;
• and
• a fourth predetermined number of fourth inverters each having a fourth pull-up transistor and a fourth pull-down transistor, the fourth pull-up transistor having a large size and the fourth pull-down transistor having a small size;
• and
• wherein the third and fourth inverters are alternately serially connected such that an output signal from a third inverter is an input signal to a fourth inverter and the third inverter in a first position is responsive to the inverted clock signal.