Semiconductor integrated circuit device
AssigneeNEC Corporation
InventorYoshinori Matsui
Life of this patent
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Abstract
The semiconductor integrated circuit device of the present invention for accepting an external signal synchronously with an external clock signal, comprises: an internal clock signal circuit for detecting a change in the external clock signal and generating an internal clock signal having a predetermined pulse width; a latch circuit for accepting the external signal in advance and latching the external signal for the period of time corresponding to the predetermined pulse width according to the internal clock signal; and an internal signal generating circuit for generating an internal signal which reflects the logic of the external signal and has the predetermined pulse width, according to the internal clock signal.
Claims6
A semiconductor integrated circuit device for accepting an external signal synchronously with an external clock signal, comprising:
- an internal clock signal circuit for detecting a change in the external clock signal and generating an internal clock signal having a predetermined pulse width;
- a latch circuit for receiving the external signal and the internal clock signal and latching the external signal for a period of time corresponding to the predetermined pulse width according to the internal clock signal;
- and
- an internal signal generating circuit for receiving the external signal from the latch circuit and the internal clock signal and generating an internal signal which reflects the logic of the external signal and has the predetermined pulse width, according to the internal clock signal.
A semiconductor integrated circuit device for accepting an external control signal synchronously with an external clock signal, comprising:
- an internal clock signal circuit for detecting a change in the external clock signal and generating an internal clock signal having a predetermined pulse width;
- a latch circuit for receiving the external control signal and the internal clock signal and latching the external control signal for a period of time corresponding to the predetermined pulse width according to the internal clock signal;
- and
- an internal control signal generating circuit for receiving the external control signal from the latch circuit and the internal clock signal and generating an internal control signal which reflects the logic of the external control signal and has the predetermined pulse width, according to the internal clock signal.
Dependencies are inferred from the claim text.