Current sense amplifier and current comparator with hysteresis

A current comparator, comprising:

• a first amplifier and a second amplifier, wherein each amplifier comprises:
• a first n-channel metal oxide semiconductor (NMOS) transistor;
• a p-channel metal oxide semiconductor (PMOS) transistor, wherein the NMOS and the PMOS transistors are coupled at a drain region;
• and
• a signal input node coupled to a source region of the NMOS transistor;
• and
• a signal output node coupled to the drain region of the NMOS and the PMOS transistors in the second amplifier, and wherein the signal output node is further coupled to a gate of a second NMOS transistor, a drain region of the second NMOS transistor is coupled to a source region of the PMOS transistor in the second amplifier, and a source region of the second NMOS transistor is coupled to the signal input node in the second amplifier.

A current sense amplifier, comprising:

• a first amplifier and a second amplifier, wherein each amplifier comprises:
• a first transistor of a first conductivity type;
• a second transistor of a second conductivity type, wherein the first and second transistors are coupled at a drain region;
• and
• a signal input node coupled to a source region of the first transistor;
• and
• a signal output node coupled to the drain region of the first and the second transistors in the second amplifier, and wherein the signal output node is further coupled to a gate of a third transistor and a fourth transistor, and wherein a drain region of the third transistor is coupled to the signal input node in at least one of the first and the second amplifiers.

An electronic system, comprising:

• a processor;
• a memory device;
• and
• a bus coupling the processor and the memory device, the memory device including a current sense amplifier, comprising:
• a first amplifier and a second amplifier, wherein each amplifier comprises:
• a first transistor of a first conductivity type;
• a second transistor of a second conductivity type,
• wherein the first and second transistors are coupled at a drain region;
• and
• a signal input node coupled to a source region of the first transistor;
• and
• a signal output node coupled to the drain region of the first and the second transistors in the second amplifier, and wherein the signal output node is further coupled to a gate of a third transistor, wherein a source region of the third transistor is coupled directly to a source region of the second transistor in the first amplifier, and wherein a drain region of the third transistor is coupled to the signal input node in at least one of the first and the second amplifiers.

An integrated circuit, comprising:

• a processor;
• a memory operatively coupled to the processor;
• and
• wherein the processor and memory are formed on the same semiconductor substrate and the integrated circuit includes at least one current sense amplifier coupled to the memory, comprising:
• a first amplifier and a second amplifier, wherein each amplifier comprises:
• a first transistor of a first conductivity type;
• a second transistor of a second conductivity type,
• wherein the first and second transistors are coupled at a drain region;
• and
• a signal input node coupled to a source region of the first transistor;
• and
• a signal output node coupled to the drain region of the first and the second transistors in the second amplifier, and wherein the signal output node is further coupled to a gate of a third transistor, wherein a source region of the third transistor is coupled directly to a source region of the second transistor in the first amplifier, and wherein a drain region of the third transistor is coupled to the signal input node in at least one of the first and the second amplifiers.

A method of forming a current sense amplifier, comprising:

• forming a first amplifier and a second amplifier, wherein the forming of each amplifier comprises:
• forming a first transistor of a first conductivity type;
• forming a second transistor of a second conductivity type, wherein the first and second transistors are coupled at a drain region;
• and
• forming a signal input node coupled to a source region of the first transistor;
• and
• forming a signal output node coupled to the drain region of the first and the second transistors in the second amplifier, and wherein the forming of the signal output node includes coupling the signal output node to a gate of a third transistor, coupling a source region of the third transistor directly to a source region of the second transistor in the first amplifier, and coupling a drain region of the third transistor to the signal input node in at least one of the first and the second amplifiers.

A method of forming a current comparator with hysteresis, comprising:

• forming a first amplifier and a second amplifier, wherein forming each amplifier comprises:
• forming a first NMOS transistor;
• forming a first PMOS transistor, wherein the first NMOS transistor and the first PMOS transistor are coupled at a drain region;
• and
• forming a signal input node coupled to a source region of the first NMOS transistor;
• and
• forming a signal output node coupled to the drain region of the first NMOS transistor and the first PMOS transistor in the second amplifier, and wherein the forming of the signal output node includes coupling the signal output node to gates of a second NMOS transistor and a second PMOS transistor, and wherein a source region of the second NMOS transistor is coupled to the signal input node in at least one of the first and the second amplifiers.

A method for operating a current sense amplifier, comprising:

• providing a current signal to a first signal input node of the current sense amplifier;
• providing a reference signal to a second signal input node of the current sense amplifier;
• providing a first feedback from a signal output of the current sense amplifier to the second signal input node;
• and
• wherein the providing of a first feedback from the signal output to the second signal input node introduces a hysteresis into the current sense amplifier in order to discriminate against noise transients and wherein the providing of a first feedback from the signal output to the second signal input node includes adjusting a high threshold voltage trip point (Tph) in the current sense amplifier.

A method for operating a current sense amplifier, comprising:

• providing a current signal to a first signal input node of the current sense amplifier;
• providing a reference signal to a second signal input node of the current sense amplifier;
• providing a feedback from a signal output of the current sense amplifier to the first signal input node through a first transistor and to the second signal input node through a second transistor;
• and
• wherein the providing of a feedback from the signal output of the current sense amplifier to the first and the second signal input nodes includes adjusting voltage thresholds for the detection of valid signals along with the rejection of small noise current transients or reflections and ringing.