Low voltage differential dual receiver

A bus interface integrated circuit for communicating values over a line of a bus, said bus line not being terminated by a bias voltage, said bus interface integrated circuit comprising:

• a plurality of bus lines, wherein all bus lines of said bus are included in said plurality of bus lines, said plurality of bus lines being arranged to transmit a first signal and to transmit a second signal that is the complement of said first signal, said first and second signals being arranged to communicate values over said plurality of bus lines, wherein said first and second input signals are connected to a common mode reference voltage;
• a low-voltage differential symmetrical driver connected to each of said plurality of bus lines and arranged to transmit a first portion of said values over said plurality of bus lines in a symmetrical fashion;
• and
• a low-voltage differential dual receiver connected to each of said plurality of bus lines and arranged to receive a second portion of said values over said plurality of bus lines, said dual receiver including
• a high-speed receiver having said first and second signals as inputs and arranged to produce said second portion of said values as high-speed outputs during a data phase of said bus, and
• a low-speed receiver having said first and second signals as inputs and arranged to produce said second portion of said values as low-speed outputs during a protocol phase of said bus, said low-speed receiver including a voltage offset such that during said protocol phase said plurality of bus lines enters a known state.

A low-voltage differential dual receiver apparatus for receiving a value over a line of a bus not being terminated by a bias voltage, said dual receiver comprising:

• a first input signal being received in said dual receiver;
• a second input signal being received in said dual receiver and being the complement of said first input signal, said first and second input signals being arranged to transmit said value over said bus line to said dual receiver, wherein said first and second input signals are connected to a common mode reference voltage;
• a high-speed differential receiver having said first and second input signals as inputs and arranged to produce said value as a high-speed output during a data phase of said bus, said high-speed differential receiver arranged to communicate with a symmetrical driver on said bus line;
• and
• a low-speed differential receiver having said first and second input signals as inputs and arranged to produce said value as a low-speed output during a protocol phase of said bus, said low-speed differential receiver including a voltage offset such that during said protocol phase said bus line enters a known state;
• a differential receiver circuit having a pair of differential transistors, a first one of said transistors being connected through a first resistor to a bias current and a second one of said transistors being connected through a second resistor to said bias current, said first and second resistors differing in value by a matching resistance, and a current matching circuit for producing said bias current, said bias current passing through a third resistor having a value equivalent to said matching resistance, whereby said voltage offset is produced by passing said bias current through said first and second resistors.