Data register circuit in memory device

Abstract

A data register circuit, comprising: input means which includes a first input portion and a second input portion, the first input portion being reset by a data reset signal and buffering a data signal from a data line in accordance with a data fetch signal and the second input portion being reset by a data reset signal and buffering a data bar signal from a data bar line in accordance with the data fetch signal; storing means which includes a first flip flop and a second flip flop, the first and second flip flops for respectively receiving output signals of the first and second input portions of the input means and providing inverting signals of the output signals of the first and second input portions until the output signals of the first and second input portions are changed by the data reset signal, a first latch which is connected between the first input portion and the first flip flop and temporarily stores the output signal of the first input portion and a second latch which is connected between the second input portion and the second flip flop and temporarily stores the output signal of the second input portion; and data output means which includes a first output portion for receiving and buffering an output signal of the first flip flop and for providing an output signal through a pull-down terminal by a data output control signal and a second output portion for receiving and buffering an output signal of the second flip flop and for providing it an output signal through a pull-up terminal by the data output control signal.

Dependencies are inferred from the claim text.