High speed buffer circuit with improved noise immunity
AssigneeIntegrated Device Technology, Inc.
InventorsChuen-Der Lien, Ta-Ke Tien
Life of this patent
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Abstract
In a buffer circuit a pull-up circuit causes an output terminal of the buffer circuit make a transition from a low voltage to a high, and a feedback circuit increases the rate of the transition during the part of the transition when the output terminal moves from the low voltage to a predesignated voltage, the predesignated voltage being a value between but different from the low and high voltages. In another buffer circuit powered by a power supply voltage, a pull-up transistor causes a signal at an output terminal of the buffer circuit make a transition from a low voltage to a high voltage, and a converter circuit converts the power supply voltage to a lower voltage, the lower voltage powering the pull-up transistor.
Claims17
A buffer circuit comprising:
- an output terminal;
- a first circuit coupled between a power supply terminal and a ground terminal for causing the output terminal to make a transition from a first voltage to a second voltage, the first circuit including a first NMOS transistor coupled between the power supply terminal and the output terminal and a second NMOS transistor coupled between the output terminal and the ground terminal;
- and
- a feedback circuit for increasing the rate of said transition during part of the transition when the output terminal moves from the first voltage to a predesignated voltage, the predesignated voltage being a value between but different from the first and second voltages, the feedback circuit including an AND gate having a first input terminal coupled to a buffer driver, a second input terminal coupled to the output terminal, and a control terminal coupled to a pull transistor, the pull transistor being coupled between one of the power supply terminal or the ground terminal and the output terminal, the pull transistor being a PMOS transistor.
A method for driving an output terminal of a buffer circuit, the method comprising:
- (A) turning on a first circuit to cause the output terminal to make a transition from a first voltage to a second voltage, the first circuit including a first NMOS transistor coupled between a power supply terminal and the output terminal and a second NMOS transistor coupled between the output terminal and a ground terminal;
- and
- (B) turning on a feedback circuit to increase the rate of said transition during part of the transition when the output terminal moves from the first voltage to a predesignated voltage, the predesignated voltage being a value between but different from the first and second voltages, the feedback circuit having an AND gate with a first input terminal coupled to a buffer driver, a second input terminal coupled to the output terminal, and a control terminal coupled to a pull transistor, the pull transistor being coupled to pull the output terminal from the first voltage to the second voltage, the pull transistor being a PMOS transistor.
Dependencies are inferred from the claim text.