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AssigneeInfineonTechnologies AG
InventorsGerhard Mueller, David R. Hanson
Estimating the term…
A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.
In an integrated circuit, a method for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals, said reduced voltage signals having a voltage level that is below VDD, said reduced voltage repeater circuit being configured to be coupled to said signal line and having an input node coupled to a first portion of said signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of said signal line for outputting a second reduced voltage signal, comprising:
In an integrated circuit, a method for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals, said reduced voltage signals having a voltage level that is below VDD, said reduced voltage repeater circuit being configured to be coupled to said signal line and having an input node coupled to a first portion of said signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of said signal line for outputting a second reduced voltage signal, comprising:
In an integrated circuit, a method for implementing a reduced voltage bi-directional repeater circuit on a signal line having thereon reduced voltage signals, said reduced voltage signals having a voltage level that is below VDD, said reduced voltage bi-directional repeater circuit being configured to be coupled to said signal line and having a first data port coupled to a first portion of said signal line and a second data port coupled to a second portion of said signal line, comprising:
A reduced voltage bi-directional repeater circuit configured to be coupled to a reduced voltage bi-directional repeater circuit on a signal line having thereon reduced voltage signals, said reduced voltage signals having a voltage level that is below VDD, said reduced voltage bi-directional repeater circuit being configured to be coupled to said signal line and having a first data port configured to be coupled to a first portion of said signal line and a second data port configured to be coupled to a second portion of said signal line, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Of non-metallic inorganic material, e.g. stone, ceramics, porcelain: of thin, brittle parts, e.g. semiconductors, wafers
Lapping machines or devices; Accessories: designed for working plane surfaces
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
Arrangements for reducing power consumption: in field effect transistor circuits
Term ended 9 Mar 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to repeater circuits for high resistance and/or high capacitance signal lines on an integrated circuit. More particularly, the present invention relates to reduced voltage input/reduced voltage output repeaters which, when employed on a high resistance and/or high capacitance signal line, reduces the signal propagation delay, power dissipation, chip area, electrical noise, and/or electromigration.
In some integrated circuits, there exist signal lines which span long distances and/or coupled to many circuits. In modern dynamic random access memory circuits, for examples, certain unidirectional signal lines such as address lines may be coupled to many circuits and may therefore have a high capacitive load and/or resistance associated therewith. Likewise, certain bi-directional lines such as read write data (RWD) lines may also be coupled to many circuits and may therefore also have a high capacitive load and/or resistance associated therewith. The same issue also applies for many signal lines in modern microprocessors, digital signal processors, or the like. By way of example, the same issue may be seen with loaded read data lines and write data lines of memory circuits, clock lines of an integrated circuit, command lines, and/or any loaded signal carrying conductor of an integrated circuit. The propagation delay times for these signal lines, if left unremedied, may be unduly high for optimal circuit performance.
To facilitate discussion, FIG. 1 illustrates an exemplary signal line 100, representing a signal conductor that may be found in a typical integrated circuit. Signal line 100 includes resistors 102 and 104, representing the distributed resistance associated with signal line 100. Resistors 102 and 104 have values which vary with, among others, the length of signal line 100. There are also shown capacitors 106 and 108, representing the distributed capacitance loads associated with the wire or signal bus and the circuits coupled to signal line 100.
The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:
FIG. 1 illustrates an exemplary signal line, representing a signal conductor that may be found in a typical integrated circuit.
FIG. 2 depicts the signal line of FIG. 1 having thereon a repeater to reduce its propagation delay FIG. 3A illustrates, in accordance with one embodiment of the present invention, a simplified reduced voltage signal tri-state buffer circuit, representing a circuit that may be employed as a reduced voltage signal unidirectional repeater.
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known structures and/or process steps have not been described in detail in order to not unnecessarily obscure the present invention.
The invention relates, in one embodiment, to a technique for improving performance in reduced voltage integrated circuits. In accordance with one aspect of the present invention, various reduced voltage tri-state buffer configurations are disclosed as being suitable candidates for unidirectional or bi-directional repeater applications. In accordance with one aspect of the present invention, reduced voltage unidirectional repeaters are employed on high resistance and/or high capacitance unidirectional line(s) of an integrated circuit to reduce the signal propagation delay, power dissipation, chip area, electrical noise, and/or electromigration. In accordance with another aspect of the present invention, reduced voltage bi-directional repeaters are employed on high resistance and/or high capacitance bi-directional line(s) of an integrated circuit to reduce the signal propagation delay, power dissipation, chip area, electrical noise, and/or electromigration of the integrated circuit.
The features and advantages of the present invention may be better understood with reference to the figures that follow. FIG. 3A illustrates, in accordance with one embodiment of the present invention, a simplified tri-state buffer circuit 200, including input stage 202, level shifting stage 204, and output stage 206. Tri-state buffer circuit 200 represents a repeater circuit suitable for use in a unidirectional low voltage input/low voltage output application. As shown, the buffer enable signal is optionally coupled to input stage 202 to control transistors therein, which pass the reduced voltage input signal on terminal 208 to level shifting stage 204. As will be shown later herein, the buffer enable signal is also employed in some embodiments to control the passage of signals within level shifter stage 204 and/or the output stage 206.