Method and apparatus for reducing the power consumption of a voltage regulator
AssigneeIntel Corporation
InventorDon J. Nguyen
Life of this patent
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AssigneeIntel Corporation
InventorDon J. Nguyen
Estimating the term…
A voltage regulator illustrating one embodiment of the apparatus of the present invention is described. The voltage regulator includes an output stage for providing an output voltage on an output voltage terminal, a first switch for charging the output stage, and a second switch for discharging output stage 201. The voltage regulator also includes an input signal terminal for receiving a control signal and a third switch for preventing the second switch from closing when the control signal is asserted. When the control signal on the input signal terminal is not asserted, the voltage regulator operates as a typical switching regulator, alternately charging and discharging the output stage to maintain a stable output voltage on the output voltage terminal. A portion of the power supplied to charge the output stage is consumed every time the output stage is discharged. However, when the control signal on the input terminal is asserted, the second switch is prevented from closing, so the output stage is not discharged through the second switch. Therefore, the power consumption of the voltage regulator is reduced.
A voltage regulator comprising:
A voltage regulator comprising:
A voltage regulator comprising:
A voltage regulator comprising:
An electronic system comprising:
An electronic system comprising:
A method of reducing the power consumption of a voltage regulator providing a supply voltage to an electronic device, said method comprising:
Dependencies are inferred from the claim text.