Plastic package for semiconductor device

A plastic package for accommodating a semiconductor chip comprising:

• (a) a first insulating layer, in which a first opening is formed to accommodate said semiconductor chip, having
• a plurality of first bonding pads, including a first power source bonding pads, formed on the obverse surface adjacent to the top of said first opening,
• a first power source plane layer formed on the reverse surface,
• a first side wall conductive layer, formed on the side wall of said first opening, for connecting said first power source bonding pad on said obverse surface to said first power source plane layer on said reverse surface,
• a plurality of first signal lines formed on the obverse surface and connected to the first bonding pads, and
• a first power source line formed on the obverse surface and connected to the first power source bonding pad, said first power source line being located between the plurality of first signal lines;
• (b) a second insulating layer, which covers said first insulating layer and in which a second opening is formed which is larger than said first opening, having
• a plurality of second bonding pads, including a second power source bonding pad which is formed on the obverse surface adjacent to the top of said second opening,
• a second power source plane layer formed on the reverse surface,
• a second side wall conductive layer, formed on the side wall of said second opening, for connecting said second power source bonding pad on said obverse surface to said second power source plane layer on said reverse surface,
• a plurality of second signal lines formed on the obverse surface and connected to the second bonding pads, and
• a second power source line formed on the obverse surface and connected to the second power source bonding pad, said second power source line being located between the plurality of second signal lines;
• (c) a support substrate provided at said first opening for mounting said semiconductor chip thereon;
• (d) a first external power source terminal for connection to said first power source plane layer and said first power source line via a first through hole;
• and
• (e) a second external power source terminal for connection to said power source plane layer and said second line via a second through hole.