Semiconductor package with a stacked chip on a leadframe

A semiconductor package, said semiconductor package comprising:

• a first leadframe having first leads;
• first adhesive material attached on an area under said first leads;
• a first chip connected to said first leadframe by first conductive bumps for electrically coupling to said first leads, wherein said first adhesive material has a surface at least larger than that of said first chip;
• a first compound filled in the space among said first chip, said first leadframe and said first conductive bumps;
• a second leadframe having second leads, wherein said first leads are connected to said second leads;
• a second adhesive material attached IQ an area under said second leads;
• a second chip connected to said second leadframe by second conductive bumps for electrically coupling to said second leads, wherein said second adhesive material has a surface at least larger than that of said second chip;
• and
• a second compound filled in the space among said second chip, said second leadframe and said second conductive bumps.

A semiconductor package, said semiconductor package comprising:

• a leadframe having a plurality of leads;
• adhesive material attached to an area under said leads, wherein said adhesive material has slots formed therein to expose terminal portions of said leads;
• a first chip connected to the upper surface of said leadframe by first conductive bumps for electrically coupling to said leads, wherein said adhesive material has an area larger than that of said first chip;
• and
• a second chip connected to the lower surface of said leadframe through said slots by second conductive bumps for electrically coupling to said leads, wherein said second chip is face to face to said first chip.