Back to results
US 6,307,236 B1Granted
Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsNozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeHitachi, Ltd.
InventorsNozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
Estimating the term…
The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.
A semiconductor integrated circuit device comprising on the same substrate a plurality of kinds of metal oxide semiconductor (MOS) transistors different in thickness of a gate insulation film, wherein said device has main circuitry constituted from at least one first MOS transistor having a gate insulation film with a first value in thickness of those of said plurality of kinds of MOS transistors, and control circuitry including at least one second MOS transistor having a gate insulation film with a second value greater than said first value in thickness, which source-drain path is inserted between said main circuitry and at least one of two power supplies of said main circuitry, wherein said control circuitry controls magnitude of leakage current flowing either between a source and a gate or between a drain and said gate of said first MOS transistor by controlling on/off state of said second MOS transistor.
A semiconductor integrated circuit device comprising a first MOS transistor having between its source and gate or between drain and gate an insulative film of a first value in thickness, and a second MOS transistor having between its source and gate or between drain and gate an insulative film a second value greater than said first value in thickness, wherein a source-drain path of said first MOS transistor is between a first node and a second node, and a source-drain path of said second MOS transistor is serially coupled to a source-drain path of said first MOS transistor and is between said second node to a third node, and wherein said second MOS transistor controls a current flowing between said first node and said third node through the source and gate of said first MOS transistor or through the drain and gate thereof.
A semiconductor integrated circuit device comprising a plurality of kinds of MOS transistors different in thickness of a gate insulation film, main circuitry including at least one first MOS transistor having a gate insulation film with a first value in thickness, and control circuitry including at least one second MOS transistor having a gate insulation film with a second value greater than said first value in thickness, which source-drain path is inserted between said main circuitry and at least one of two power supplies of said main circuitry, wherein flow of a source-to-gate current or drain-to-gate current of the first MOS transistor is controlled by changing on/off state of said second MOS transistor in response to a control signal as supplied to said control circuitry.
A semiconductor integrated circuit device comprising:
Dependencies are inferred from the claim text.