Another technique for gated lateral bipolar transistors

A low voltage transistor providing simultaneous bipolar junction transistor (BJT) type conduction and metal oxide semiconductor (MOS) type conduction, comprising:

• a semiconductor structure having an upper surface and opposing sidewall surfaces, the semiconductor structure having a source region, a body region, and having a drain region, the source region and the drain region located on a first one of the opposing sidewall surfaces;
• a dielectric layer disposed between the source region and the drain region on the first one of the opposing sidewall surfaces;
• a gate formed on the dielectric layer on the first one of the opposing sidewall surfaces;
• and
• a body contact coupled to the body region on a second one of the opposing sidewall surfaces, such that the transistor exhibits bipolar junction transistor (BJT) action in addition to metal-oxide semiconductor (MOS) action.

A transistor, comprising:

• a semiconductor structure having an upper surface and opposing sidewall surfaces, the semiconductor structure having a source region, a body region, and having a drain region, the source region and the drain region located on the upper surface, on a first one of the opposing sidewall surfaces, and on a second one of the opposing sidewall surfaces, and wherein the body region of the semiconductor structure is formed on an insulator layer;
• a dielectric layer disposed between the source region and the drain region on the first one of the opposing sidewall surfaces;
• a gate formed on the dielectric layer on the first one of the opposing sidewall surfaces;
• and
• a body contact coupled to the body region on a second one of the opposing sidewall surfaces, such that the transistor exhibits simultaneous bipolar junction transistor (BJT) and metal-oxide semiconductor (MOS) action.

A low voltage integrated circuit including a number of gated lateral bipolar transistors, each gated lateral bipolar transistor comprising:

• a semiconductor structure having an upper surface and opposing sidewall surfaces, the semiconductor structure having a source region, a body region, and having a drain region, the source region and the drain region located on the upper surface, on a first one of the opposing sidewall surfaces, and on a second one of the opposing sidewall surfaces, and wherein the body region of the semiconductor structure is formed on an insulator layer;
• a dielectric layer disposed between the source region and the drain region on the first one of the opposing sidewall surfaces;
• a gate formed on the dielectric layer on the first one of the opposing sidewall surfaces;
• and
• a body contact coupled to the body region on a second one of the opposing sidewall surfaces, wherein the body contact is more highly doped than the body/base region of the single crystalline semiconductor structure such that the transistor exhibits simultaneous bipolar junction transistor (BJT) and metal-oxide semiconductor (MOS) action.